From patchwork Wed Jun 15 16:37:51 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9178953 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 238AA604DB for ; Wed, 15 Jun 2016 16:38:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 14B9826538 for ; Wed, 15 Jun 2016 16:38:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0898527DCE; Wed, 15 Jun 2016 16:38:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 64FFB26538 for ; Wed, 15 Jun 2016 16:38:55 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bDDqA-0005AP-7u; Wed, 15 Jun 2016 16:38:54 +0000 Received: from mail-pf0-x229.google.com ([2607:f8b0:400e:c00::229]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1bDDpz-00052F-QM for linux-rockchip@lists.infradead.org; Wed, 15 Jun 2016 16:38:45 +0000 Received: by mail-pf0-x229.google.com with SMTP id t190so10388198pfb.3 for ; Wed, 15 Jun 2016 09:38:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=WBFlwsXmhYOWdM9NHJTGxXtBcCtPNNUD0K3Vae1l+KM=; b=TnfI47XdqRsTh07N0yHoD5/ZbiuFf/JYhQAYWlIaZBRIA/cVJnnGIQTw53XSX7E2Ig ljlwj7Wjhe1QanMIhxvu6yCStJwVOrJOyHeHdMv1ThthIvCk+VjVWhMexpLYJFtuc0pJ vs7kHixV8U0PaFAlUmRtFJ//qi9wOZc10/2Ug= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WBFlwsXmhYOWdM9NHJTGxXtBcCtPNNUD0K3Vae1l+KM=; b=JDllbSfBtDAsUJ78YV8e/AYVALrT2KUHVLZOhgiQyc1GkiC5pzg57DnV+AKgM2WcwU tHoGZH6XnubFtWp9usb2qHnuOymHX3PSaYm/FgogrHz74F2ztS1c+quiqUjpoiCwzX3L 7gltwXSnTnX44fATk18lB12N08RzUNbwiTgsZIAqM/gbT1zWVY6sEBe0zSmrTrHU5xMC fP+Vz3dH+kw2FW0gQWUVdcr1SGsQPQaNzfJdbKzQO27FlSfHS+CRSqheINBy64XR4JBy fGTbL5TereTSkjtIqW0dCYx6f8MwONnYZo1Fe1eNbw2s4hG4Ijg/5CW9GOcrcSrcPVxQ zPWQ== X-Gm-Message-State: ALyK8tJNlIvD8QV0iPqIPscSuCIdxXylWMK8D5b42IOSemMpKT5Ie5qqroTRzQz72FDastWN X-Received: by 10.98.27.141 with SMTP id b135mr4697978pfb.111.1466008702549; Wed, 15 Jun 2016 09:38:22 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id l123sm54281501pfl.21.2016.06.15.09.38.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 15 Jun 2016 09:38:21 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Subject: [PATCH v2.1 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Date: Wed, 15 Jun 2016 09:37:51 -0700 Message-Id: <1466008675-9357-8-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160615_093843_915669_4C1A8394 X-CRM114-Status: GOOD ( 23.23 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Douglas Anderson , shawn.lin@rock-chips.com, adrian.hunter@intel.com, wsa+renesas@sang-engineering.com, luisbg@osg.samsung.com, groeck@chromium.org, stefan.wahren@i2se.com, briannorris@chromium.org, michal.simek@xilinx.com, linux-rockchip@lists.infradead.org, geert@linux-m68k.org, soren.brinkmann@xilinx.com, yangbo.lu@freescale.com, devicetree@vger.kernel.org, swarren@wwwdotorg.org, horms+renesas@verge.net.au, chaotian.jing@mediatek.com, linux-arm-kernel@lists.infradead.org, xzy.xu@rock-chips.com, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, andrei.pistirica@microchip.com, ludovic.desroches@atmel.com MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work with arasan,sdhci-5.1) need to know the card clock in order to function properly. Let's add the ability to expose this clock. Any PHY that needs to know the clock rate can add a reference and query the clock rate. At the moment we register a CLK_GET_RATE_NOCACHE clock that simply allows querying the clock. This allows us to be less intrusive with regards to the main SDHCI driver, which has complex logic for adjusting the SD clock. Right now we always fully power cycle the PHY when the clock changes and that gives the PHY a good chance to query our clock. Signed-off-by: Douglas Anderson Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- Note: just sending the one quick fix as v2.1. If further spins are needed I'll send out a full v3. Changes in v2.1: - Add dependency on COMMON_CLK (Guenter Roeck) Changes in v2: None drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-of-arasan.c | 125 ++++++++++++++++++++++++++++++++++++- 2 files changed, 123 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 0aa484c10c0a..6725dc9e644b 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -122,6 +122,7 @@ config MMC_SDHCI_OF_ARASAN tristate "SDHCI OF support for the Arasan SDHCI controllers" depends on MMC_SDHCI_PLTFM depends on OF + depends on COMMON_CLK help This selects the Arasan Secure Digital Host Controller Interface (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC. diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 1286fe8905dc..678f316702e0 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -19,6 +19,7 @@ * your option) any later version. */ +#include #include #include #include @@ -73,17 +74,24 @@ struct sdhci_arasan_soc_ctl_map { /** * struct sdhci_arasan_data + * @host: Pointer to the main SDHCI host structure. * @clk_ahb: Pointer to the AHB clock * @phy: Pointer to the generic phy * @phy_on: True if the PHY is turned on. + * @sdcardclk_hw: Struct for the clock we might provide to a PHY. + * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. * @soc_ctl_map: Map to get offsets into soc_ctl registers. */ struct sdhci_arasan_data { + struct sdhci_host *host; struct clk *clk_ahb; struct phy *phy; bool phy_on; + struct clk_hw sdcardclk_hw; + struct clk *sdcardclk; + struct regmap *soc_ctl_base; const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; }; @@ -307,6 +315,31 @@ static const struct of_device_id sdhci_arasan_of_match[] = { MODULE_DEVICE_TABLE(of, sdhci_arasan_of_match); /** + * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate + * + * Return the current actual rate of the SD card clock. This can be used + * to communicate with out PHY. + * + * @hw: Pointer to the hardware clock structure. + * @parent_rate The parent rate (should be rate of clk_xin). + * Returns the card clock rate. + */ +static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) + +{ + struct sdhci_arasan_data *sdhci_arasan = + container_of(hw, struct sdhci_arasan_data, sdcardclk_hw); + struct sdhci_host *host = sdhci_arasan->host; + + return host->mmc->actual_clock; +} + +static const struct clk_ops arasan_sdcardclk_ops = { + .recalc_rate = sdhci_arasan_sdcardclk_recalc_rate, +}; + +/** * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq * * The corecfg_baseclkfreq is supposed to contain the MHz of clk_xin. This @@ -345,6 +378,83 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host) sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); } +/** + * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use + * + * Some PHY devices need to know what the actual card clock is. In order for + * them to find out, we'll provide a clock through the common clock framework + * for them to query. + * + * Note: without seriously re-architecting SDHCI's clock code and testing on + * all platforms, there's no way to create a totally beautiful clock here + * with all clock ops implemented. Instead, we'll just create a clock that can + * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock + * framework that we're doing things behind its back. This should be sufficient + * to create nice clean device tree bindings and later (if needed) we can try + * re-architecting SDHCI if we see some benefit to it. + * + * @sdhci_arasan: Our private data structure. + * @clk_xin: Pointer to the functional clock + * @dev: Pointer to our struct device. + * Returns 0 on success and error value on error + */ +static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan, + struct clk *clk_xin, + struct device *dev) +{ + struct device_node *np = dev->of_node; + struct clk_init_data sdcardclk_init; + const char *parent_clk_name; + int ret; + + /* Providing a clock to the PHY is optional; no error if missing */ + if (!of_find_property(np, "#clock-cells", NULL)) + return 0; + + ret = of_property_read_string_index(np, "clock-output-names", 0, + &sdcardclk_init.name); + if (ret) { + dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); + return ret; + } + + parent_clk_name = __clk_get_name(clk_xin); + sdcardclk_init.parent_names = &parent_clk_name; + sdcardclk_init.num_parents = 1; + sdcardclk_init.flags = CLK_GET_RATE_NOCACHE; + sdcardclk_init.ops = &arasan_sdcardclk_ops; + + sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init; + sdhci_arasan->sdcardclk = + devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw); + sdhci_arasan->sdcardclk_hw.init = NULL; + + ret = of_clk_add_provider(np, of_clk_src_simple_get, + sdhci_arasan->sdcardclk); + if (ret) + dev_err(dev, "Failed to add clock provider\n"); + + return ret; +} + +/** + * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk() + * + * Should be called any time we're exiting and sdhci_arasan_register_sdclk() + * returned success. + * + * @dev: Pointer to our struct device. + */ +static void sdhci_arasan_unregister_sdclk(struct device *dev) +{ + struct device_node *np = dev->of_node; + + if (!of_find_property(np, "#clock-cells", NULL)) + return; + + of_clk_del_provider(dev->of_node); +} + static int sdhci_arasan_probe(struct platform_device *pdev) { int ret; @@ -362,6 +472,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + sdhci_arasan->host = host; match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); sdhci_arasan->soc_ctl_map = match->data; @@ -411,10 +522,14 @@ static int sdhci_arasan_probe(struct platform_device *pdev) sdhci_arasan_update_baseclkfreq(host); + ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); + if (ret) + goto clk_disable_all; + ret = mmc_of_parse(host->mmc); if (ret) { dev_err(&pdev->dev, "parsing dt failed (%u)\n", ret); - goto clk_disable_all; + goto unreg_clk; } sdhci_arasan->phy = ERR_PTR(-ENODEV); @@ -425,13 +540,13 @@ static int sdhci_arasan_probe(struct platform_device *pdev) if (IS_ERR(sdhci_arasan->phy)) { ret = PTR_ERR(sdhci_arasan->phy); dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); - goto clk_disable_all; + goto unreg_clk; } ret = phy_init(sdhci_arasan->phy); if (ret < 0) { dev_err(&pdev->dev, "phy_init err.\n"); - goto clk_disable_all; + goto unreg_clk; } host->mmc_host_ops.hs400_enhanced_strobe = @@ -447,6 +562,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev) err_add_host: if (!IS_ERR(sdhci_arasan->phy)) phy_exit(sdhci_arasan->phy); +unreg_clk: + sdhci_arasan_unregister_sdclk(&pdev->dev); clk_disable_all: clk_disable_unprepare(clk_xin); clk_dis_ahb: @@ -469,6 +586,8 @@ static int sdhci_arasan_remove(struct platform_device *pdev) phy_exit(sdhci_arasan->phy); } + sdhci_arasan_unregister_sdclk(&pdev->dev); + ret = sdhci_pltfm_unregister(pdev); clk_disable_unprepare(clk_ahb);