From patchwork Wed Jun 22 10:13:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 9192357 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AA1916075C for ; Wed, 22 Jun 2016 10:14:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 983BE2819A for ; Wed, 22 Jun 2016 10:14:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C950283E9; Wed, 22 Jun 2016 10:14:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B10632819A for ; Wed, 22 Jun 2016 10:14:35 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bFfB5-0004dO-E6; Wed, 22 Jun 2016 10:14:35 +0000 Received: from mail-pf0-f196.google.com ([209.85.192.196]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bFfB3-0004WF-9M for linux-rockchip@lists.infradead.org; Wed, 22 Jun 2016 10:14:34 +0000 Received: by mail-pf0-f196.google.com with SMTP id 66so3761049pfy.1 for ; Wed, 22 Jun 2016 03:14:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7XxnQ2NFNZrSf0PwtXpHM3P98SAeC7iZIiyhcw9pRI8=; b=dKOUG5sEWdnuEP+MJRvQ1RhRhxMcdhlOAYeqn/EzmqRWqwQ7llZo5Vg4NrdjKEaBFx XUeCswGjeg99dpbtS7a0Bz2YIFY/SM/t/uvbtPXjMdK2ok5qM1mw47HQBn846eKW8ZcW Pkd0zi7nWvt0M6ZvOwmplZyR7MonOiwMRLcxiLOVdD5yAmDkhNcg1GH+INFurSWCo1GU 70LK7xUfg5LWYQpvklkjSfl/9RR9xbd0KtSYIssNHJgVslyUilHK+K+Xp8hOy13tSzwg SJux4nIF0gcRANik/OU9eZGumKRquysdlIisMN9pnix1G1C7DQPMgM9pbuBWsR0tCRd7 WsTw== X-Gm-Message-State: ALyK8tKo5rFE6Z4TMUX0IaE7+wkcM3rRuVwtksgOvSJD5W7FcH/5gt6ZBloz3pEP6nIjcg== X-Received: by 10.98.43.7 with SMTP id r7mr33731724pfr.65.1466590452450; Wed, 22 Jun 2016 03:14:12 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id i124sm41363768pfg.77.2016.06.22.03.14.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 22 Jun 2016 03:14:11 -0700 (PDT) From: Caesar Wang To: edubezval@gmail.com, linux-pm@vger.kernel.org Subject: [PATCH 2/2] thermal: rockchip: fixes the exception interrupts Date: Wed, 22 Jun 2016 18:13:57 +0800 Message-Id: <1466590437-15912-2-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1466590437-15912-1-git-send-email-wxt@rock-chips.com> References: <1466584925-4829-1-git-send-email-wxt@rock-chips.com> <1466590437-15912-1-git-send-email-wxt@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160622_031433_358939_EFC57B16 X-CRM114-Status: GOOD ( 13.37 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangtao@rock-chips.com, heiko@sntech.de, linux-kernel@vger.kernel.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, smbarber@google.com, cf@rock-chips.com, rui.zhang@intel.com, rocky.hao@rock-chips.com, Caesar Wang MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The hardware-tracked trips will set the alarm interrupt value for registers. Then when the thermal zone has no trips to be set, That make the thermal trips callback a over range value. The root cause is the rk_tsadcv2_temp_to_code() function to handle the invalid temperature range is indeed incorrect, let's fix it on now. Otherwise, the thermal alarm interrupt will be triggered all the time on some SoCs. Fox example: localhost tmp # grep thermal /proc/interrupts; sleep 5; grep thermal /proc/interrupts 23: 994830 .. GICv3 129 Level rockchip_thermal 23: 1003423 .. GICv3 129 Level rockchip_thermal Reported-by: Rocky Hao Signed-off-by: Caesar Wang Cc: Zhang Rui Cc: Eduardo Valentin Cc: Heiko Stuebner Cc: linux-pm@vger.kernel.org --- Changes in v1: None drivers/thermal/rockchip_thermal.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 2d5ba97..db5ecc5 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -401,13 +401,17 @@ static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, int temp) { int high, low, mid; + u32 error = 0; low = 0; high = table.length - 1; mid = (high + low) / 2; - if (temp < table.id[low].temp || temp > table.id[high].temp) - return 0; + /* Return mask code data when the temp is over table range */ + if (temp < table.id[low].temp || temp > table.id[high].temp) { + error = table.data_mask; + goto exit; + } while (low <= high) { if (temp == table.id[mid].temp) @@ -419,7 +423,9 @@ static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, mid = (low + high) / 2; } - return 0; +exit: + pr_err("Invalid the conversion, error=%d\n", error); + return error; } static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, @@ -651,7 +657,11 @@ static void rk_tsadcv2_alarm_temp(struct chip_tsadc_table table, { u32 alarm_value, int_en; + /* Make sure the value is valid */ alarm_value = rk_tsadcv2_temp_to_code(table, temp); + if (alarm_value == table.data_mask) + return; + writel_relaxed(alarm_value & table.data_mask, regs + TSADCV2_COMP_INT(chn)); @@ -665,7 +675,11 @@ static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table, { u32 tshut_value, val; + /* Make sure the value is valid */ tshut_value = rk_tsadcv2_temp_to_code(table, temp); + if (tshut_value == table.data_mask) + return; + writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); /* TSHUT will be valid */