From patchwork Mon Jun 27 17:39:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9201025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id EB452607D3 for ; Mon, 27 Jun 2016 17:40:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE4B828597 for ; Mon, 27 Jun 2016 17:40:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D2CE2285AB; Mon, 27 Jun 2016 17:40:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6EDE128597 for ; Mon, 27 Jun 2016 17:40:24 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHaWF-0005No-TC; Mon, 27 Jun 2016 17:40:23 +0000 Received: from mail-pa0-x236.google.com ([2607:f8b0:400e:c03::236]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bHaW6-00049h-Ve for linux-rockchip@lists.infradead.org; Mon, 27 Jun 2016 17:40:16 +0000 Received: by mail-pa0-x236.google.com with SMTP id wo6so61054399pac.3 for ; Mon, 27 Jun 2016 10:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NuhgqE86CE0lB1SanK1fy60T7gTjE3Owdq7h/dsWbbM=; b=WDtrLfw//mbdhV+Fx2d8zccAWE7tSGL0lAPXvK15mwhD0+gWkyub6JRx7Ob8Hx+d58 iCB5AJGGmykQzwZP3+evhbVLsyicpiw3GCj4oc0+QThjnPM67tkjfkDKIh7k3svPqn+d hoEjjFJqxTYqg5buJGb9lVXgSrG6BIdPMjUjM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NuhgqE86CE0lB1SanK1fy60T7gTjE3Owdq7h/dsWbbM=; b=NgcfsazRg2F9st6bZnaFUTAC5CpsxouxgywBrz5LAgOE+TnNSoymX/RCmd7eGX+bYs vMXMUpdkglAYXd1revLMklD5VrQkeihJ+Lt3cAdc5ZtHyUiT22Dmh8vm89Qc55N5fcfi LsTCjHBHREbDlE4uMkkPqONjbsT6/Dj5kO/XmnEsXqC5euJI7V4v55Guqa/Ebvh7go/D mKgnAcB0Isq9c9A7anjfMz8NBk4CkYEvZw5pn1VFOcCqS0RF0BhUcBh5mQ9co3b8OsoP uaPhwJMuL+jaDWgCdAi4WFU/BYO4f7df7T7yh5x8J6YxozzmVDikJqDfx5MO/7rBvn0C tSZQ== X-Gm-Message-State: ALyK8tIHbqWwJ0xEEynnXktenyohwrjrDzqdPZ1jaBHx4LJY6y72ChlR/bZx/6LoW3tqwEac X-Received: by 10.66.89.34 with SMTP id bl2mr36293579pab.80.1467049194175; Mon, 27 Jun 2016 10:39:54 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id z29sm1120552pff.0.2016.06.27.10.39.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 27 Jun 2016 10:39:53 -0700 (PDT) From: Douglas Anderson To: Heiko Stuebner , ulf.hansson@linaro.org, kishon@ti.com Subject: [PATCH 1/3] mmc: sdhci-of-arasan: Revert: Always power the PHY off/on when clock changes Date: Mon, 27 Jun 2016 10:39:25 -0700 Message-Id: <1467049167-14628-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1467049167-14628-1-git-send-email-dianders@chromium.org> References: <1467049167-14628-1-git-send-email-dianders@chromium.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160627_104015_043318_055F1817 X-CRM114-Status: GOOD ( 17.41 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, shawn.lin@rock-chips.com, briannorris@chromium.org, linux-mmc@vger.kernel.org, Douglas Anderson , michal.simek@xilinx.com, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, adrian.hunter@intel.com, soren.brinkmann@xilinx.com MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This reverts commit 4ac0d5f245e1 ("mmc: sdhci-of-arasan: Always power the PHY off/on when clock changes"), resolving conflicts with other patches that have come after. It appears that on some boards / with some eMMC devices that the patch is causing problems. Presumably turning the phy off and on again at the wrong time while initially setting up the card is confusing the card, the host, or the PHY. We have lots of power cycles while initially setting up the card because the main sdhci driver often turns off the clock by clearing SDHCI_CLOCK_CARD_EN and then calls host->ops->set_clock() to set the clock again. With all of those, we ended up with lots of power cycles. Presumably the arguments made in the original patch still hold. That is, whenever the card clock is turned off and on again (or changed) we really should wait for the DLL to lock again. However, perhaps it's really not that critical for the lower speeds. It's possible that the right answer here is: * Whenever set_clock() is called we should double-check that the DLL is locked. * Whenever set_clock() is called and we're actually changing clocks we should do a power cycle around that. * When we're doing a power cycle just because the clock changed, we probably shouldn't do quite as many things (maybe don't need to recalibarate, etc). Unfortunately the interaction between SDHCI and the PHY is extremely limited because of the limited PHY API. The PHY does have a reference to the card clock and could theoretically register for notifications, except that our clock is query only (it uses CLK_GET_RATE_NOCACHE) and so can't really be notified about updates. I believe we would need a major redesign of clock handling in SDHCI core to do better than that, or we would need to make our one fake notifications. :( Let's hope that we can eventually get more information from Arasan on how all this should be handled before doing tons more work. Until then, let's get back to a known working state. Note that the rest of the patches in the 150 MHz series should still work fine even without this one. Signed-off-by: Douglas Anderson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-arasan.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 678f316702e0..e0f193f7e3e5 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -77,7 +77,6 @@ struct sdhci_arasan_soc_ctl_map { * @host: Pointer to the main SDHCI host structure. * @clk_ahb: Pointer to the AHB clock * @phy: Pointer to the generic phy - * @phy_on: True if the PHY is turned on. * @sdcardclk_hw: Struct for the clock we might provide to a PHY. * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw. * @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers. @@ -87,7 +86,6 @@ struct sdhci_arasan_data { struct sdhci_host *host; struct clk *clk_ahb; struct phy *phy; - bool phy_on; struct clk_hw sdcardclk_hw; struct clk *sdcardclk; @@ -170,10 +168,12 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + bool ctrl_phy = false; - if (sdhci_arasan->phy_on && !IS_ERR(sdhci_arasan->phy)) { - sdhci_arasan->phy_on = false; + if (clock > MMC_HIGH_52_MAX_DTR && (!IS_ERR(sdhci_arasan->phy))) + ctrl_phy = true; + if (ctrl_phy) { spin_unlock_irq(&host->lock); phy_power_off(sdhci_arasan->phy); spin_lock_irq(&host->lock); @@ -181,9 +181,7 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_set_clock(host, clock); - if (host->mmc->actual_clock && !IS_ERR(sdhci_arasan->phy)) { - sdhci_arasan->phy_on = true; - + if (ctrl_phy) { spin_unlock_irq(&host->lock); phy_power_on(sdhci_arasan->phy); spin_lock_irq(&host->lock); @@ -549,6 +547,12 @@ static int sdhci_arasan_probe(struct platform_device *pdev) goto unreg_clk; } + ret = phy_power_on(sdhci_arasan->phy); + if (ret < 0) { + dev_err(&pdev->dev, "phy_power_on err.\n"); + goto err_phy_power; + } + host->mmc_host_ops.hs400_enhanced_strobe = sdhci_arasan_hs400_enhanced_strobe; } @@ -561,6 +565,9 @@ static int sdhci_arasan_probe(struct platform_device *pdev) err_add_host: if (!IS_ERR(sdhci_arasan->phy)) + phy_power_off(sdhci_arasan->phy); +err_phy_power: + if (!IS_ERR(sdhci_arasan->phy)) phy_exit(sdhci_arasan->phy); unreg_clk: sdhci_arasan_unregister_sdclk(&pdev->dev);