From patchwork Sun Aug 21 19:31:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ayaka X-Patchwork-Id: 9292665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2425D607FF for ; Sun, 21 Aug 2016 19:32:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1433A28971 for ; Sun, 21 Aug 2016 19:32:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 08A9E289A1; Sun, 21 Aug 2016 19:32:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BE67E28971 for ; Sun, 21 Aug 2016 19:32:28 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bbYTs-00067V-71; Sun, 21 Aug 2016 19:32:28 +0000 Received: from kozue.soulik.info ([108.61.200.231]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bbYTq-00062F-7L for linux-rockchip@lists.infradead.org; Sun, 21 Aug 2016 19:32:26 +0000 Received: from ritsuko.sumomo.pri (unknown [IPv6:2001:470:b30d:2::3bd]) by kozue.soulik.info (Postfix) with ESMTPA id 56D9D1012EF; Mon, 22 Aug 2016 04:34:05 +0900 (JST) From: Randy Li To: linux-usb@vger.kernel.org Subject: [RESEND PATCH 4/4] ARM: dts: rockchip: Point rk3288 dwc2 usb at the full PHY reset Date: Mon, 22 Aug 2016 03:31:45 +0800 Message-Id: <1471807905-11323-2-git-send-email-ayaka@soulik.info> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1471807905-11323-1-git-send-email-ayaka@soulik.info> References: <4c931176-a09a-546c-d2b6-ea74028c78a2@cogentembedded.com> <1471807905-11323-1-git-send-email-ayaka@soulik.info> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160821_123226_444275_E006186C X-CRM114-Status: UNSURE ( 4.62 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, heiko@sntech.de, johnyoun@synopsys.com, gregkh@linuxfoundation.org, Randy Li , randy.li@rock-chips.com, linux-kernel@vger.kernel.org, kishon@ti.com, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, eddie.cai@rock-chips.com MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The "host1" port (AKA the dwc2 port that isn't the OTG port) on rk3288 has a hardware errata that causes everything to get confused when we get a remote wakeup. We'll use the reset that's in the CRU to reset the port when it's in a bad state. Note that we add the reset to both dwc2 controllers even though only one has the errata in case we find some other use for this reset that's unrelated to the current hardware errata. Only the host port gets the quirk property, though. Signed-off-by: Randy Li --- arch/arm/boot/dts/rk3288.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 48ca4e4..de54604 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -855,6 +855,8 @@ clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; #clock-cells = <0>; + resets = <&cru SRST_USBOTG_PHY>; + reset-names = "phy-reset"; }; usbphy1: usb-phy@334 { @@ -871,6 +873,8 @@ clocks = <&cru SCLK_OTGPHY2>; clock-names = "phyclk"; #clock-cells = <0>; + resets = <&cru SRST_USBHOST1_PHY>; + reset-names = "phy-reset"; }; }; };