@@ -141,6 +141,7 @@
#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
#define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
+#define PCIE_RC_CONFIG_LCS_CCC BIT(6)
#define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
#define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
#define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
@@ -540,6 +541,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip_pcie)
rockchip_pcie_set_power_limit(rockchip_pcie);
+ /* Set RC's clock architecture as common clock */
+ status = rockchip_pcie_readl(rockchip_pcie, PCIE_RC_CONFIG_LCS);
+ status |= PCIE_RC_CONFIG_LCS_CCC;
+ rockchip_pcie_writel(rockchip_pcie, PCIE_RC_CONFIG_LCS, status);
+
/* Enable Gen1 training */
rockchip_pcie_writel(rockchip_pcie, PCIE_CLIENT_CONFIG,
PCIE_CLIENT_LINK_TRAIN_ENABLE);
The default value of common clock configuration is zero indicating Rockchip's RC is using asynchronous clock architecture but actually we are using common clock. This will confuses some EP drivers if they need some different settings referring to this value. So let's fix it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> --- Changes in v3: - rebase the code since it isn't cleanly applied again Changes in v2: - rebase the code since it isn't cleanly applied after Bjorn's cleanup drivers/pci/host/pcie-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+)