From patchwork Wed Oct 12 02:05:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 9371943 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7A1C960487 for ; Wed, 12 Oct 2016 01:59:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 67700290CF for ; Wed, 12 Oct 2016 01:59:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5A85829154; Wed, 12 Oct 2016 01:59:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0ED21290CF for ; Wed, 12 Oct 2016 01:59:18 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bu8pB-0005S1-DA; Wed, 12 Oct 2016 01:59:17 +0000 Received: from lucky1.263xmail.com ([211.157.147.133]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bu8p8-0005Nv-Uq for linux-rockchip@lists.infradead.org; Wed, 12 Oct 2016 01:59:16 +0000 Received: from shawn.lin?rock-chips.com (unknown [192.168.167.164]) by lucky1.263xmail.com (Postfix) with ESMTP id 39FD854324; Wed, 12 Oct 2016 09:58:51 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED4: 1 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 7D95D3D0; Wed, 12 Oct 2016 09:58:50 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: bhelgaas@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <948b8f41d4f38ab5cf2f3f8bac5dc15e> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 10104EAZH8W; Wed, 12 Oct 2016 09:58:51 +0800 (CST) From: Shawn Lin To: Bjorn Helgaas Subject: [PATCH v3 2/3] PCI: rockchip: Mark RC as common clock architecture Date: Wed, 12 Oct 2016 10:05:02 +0800 Message-Id: <1476237903-15076-2-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1476237903-15076-1-git-send-email-shawn.lin@rock-chips.com> References: <1476237903-15076-1-git-send-email-shawn.lin@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161011_185915_661579_91CC7FD6 X-CRM114-Status: UNSURE ( 6.38 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Wenrui Li , linux-pci@vger.kernel.org, Shawn Lin , Brian Norris , linux-rockchip@lists.infradead.org, Rajat Jain MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The default value of common clock configuration is zero indicating Rockchip's RC is using asynchronous clock architecture but actually we are using common clock. This will confuses some EP drivers if they need some different settings referring to this value. So let's fix it. Signed-off-by: Shawn Lin --- Changes in v3: - rebase the code since it isn't cleanly applied again Changes in v2: - rebase the code since it isn't cleanly applied after Bjorn's cleanup drivers/pci/host/pcie-rockchip.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index a67ff9e..d51afe6 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -141,6 +141,7 @@ #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5) +#define PCIE_RC_CONFIG_LCS_CCC BIT(6) #define PCIE_RC_CONFIG_LCS_LBMIE BIT(10) #define PCIE_RC_CONFIG_LCS_LABIE BIT(11) #define PCIE_RC_CONFIG_LCS_LBMS BIT(30) @@ -540,6 +541,11 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip_pcie) rockchip_pcie_set_power_limit(rockchip_pcie); + /* Set RC's clock architecture as common clock */ + status = rockchip_pcie_readl(rockchip_pcie, PCIE_RC_CONFIG_LCS); + status |= PCIE_RC_CONFIG_LCS_CCC; + rockchip_pcie_writel(rockchip_pcie, PCIE_RC_CONFIG_LCS, status); + /* Enable Gen1 training */ rockchip_pcie_writel(rockchip_pcie, PCIE_CLIENT_CONFIG, PCIE_CLIENT_LINK_TRAIN_ENABLE);