From patchwork Wed Sep 13 10:52:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 9951029 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D7D3C6024A for ; Wed, 13 Sep 2017 10:54:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C74FA28CEC for ; Wed, 13 Sep 2017 10:54:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BB06028EEC; Wed, 13 Sep 2017 10:54:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_MED,RCVD_IN_SORBS_SPAM,RCVD_IN_SORBS_WEB autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4A1D728CEC for ; Wed, 13 Sep 2017 10:54:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=zQXkn/ITgOuaCbrVUYuZHn1FKUSfwQrHeMT0YAwYI+U=; b=TzIVoM2Y5PDVCojk0EjEjLZbtF MfqetRfkFqexTdCOMeserlUR7fJ1TEI6Ew9sAsDm6AxorAAy+Abk828H7ZwSTP89AaGrPD16YTPM9 zCDtdb7rX0A7FZR9lyfJp3MFjGNTKH/ohx5d6rfYeR377JwXS/FDiOnCoK08UwRbs5Da/Xcd1qMxX QXdIWiUNYKGyvZKVDQKkE+94G8i96Hv8465Sw8GEGtHOg1uwzotAHikGh1+/fnTfT8zf8meWYl0n5 8/150o6TKgdWNCFTyuaO478PZsEhCjoNqoavkehdwpX6P3pv4kTbTQ4MBp8mtW2xtUGva223xtUZZ NRKdPo6g==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1ds5Iz-0003LB-9T; Wed, 13 Sep 2017 10:54:05 +0000 Received: from lucky1.263xmail.com ([211.157.147.133]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1ds5Ir-0002fr-46 for linux-rockchip@lists.infradead.org; Wed, 13 Sep 2017 10:54:02 +0000 Received: from david.wu?rock-chips.com (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id 3EF528FAE7; Wed, 13 Sep 2017 18:53:31 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 28CAB3AE; Wed, 13 Sep 2017 18:53:31 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: sjg@chromium.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <88eeaa8984978d9e15fb9984a78e8e38> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 157450BDBC5; Wed, 13 Sep 2017 18:53:32 +0800 (CST) From: David Wu To: sjg@chromium.org, philipp.tomsich@theobroma-systems.com Subject: [PATCH 5/8] clk: rockchip: Add rk3328 Saradc clock support Date: Wed, 13 Sep 2017 18:52:49 +0800 Message-Id: <1505299969-13329-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505297379-12638-1-git-send-email-david.wu@rock-chips.com> References: <1505297379-12638-1-git-send-email-david.wu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170913_035357_674766_513F76B0 X-CRM114-Status: UNSURE ( 7.22 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangtao@rock-chips.com, heiko@sntech.de, u-boot@lists.denx.de, zhangqing@rock-chips.com, kever.yang@rock-chips.com, linux-rockchip@lists.infradead.org, p.marczak@samsung.com, David Wu , andy.yan@rock-chips.com, chenjh@rock-chips.com MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). Saradc integer divider control register is 10-bits width. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/clk/rockchip/clk_rk3328.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index c3a6650..e1ae7b2 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -115,6 +115,7 @@ enum { /* CLKSEL_CON23 */ CLK_SARADC_DIV_CON_SHIFT = 0, CLK_SARADC_DIV_CON_MASK = 0x3ff << CLK_SARADC_DIV_CON_SHIFT, + CLK_SARADC_DIV_CON_WIDTH = 10, /* CLKSEL_CON24 */ CLK_PWM_PLL_SEL_CPLL = 0, @@ -180,6 +181,11 @@ enum { #define PLL_DIV_MIN 16 #define PLL_DIV_MAX 3200 +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift) +{ + return (val >> shift) & ((1 << width) - 1); +} + /* * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): * Formulas also embedded within the Fractional PLL Verilog model: @@ -478,6 +484,31 @@ static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz) return DIV_TO_RATE(GPLL_HZ, div); } +static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[23]); + div = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH, + CLK_SARADC_DIV_CON_SHIFT); + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) +{ + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[23], + CLK_SARADC_DIV_CON_MASK, + src_clk_div << CLK_SARADC_DIV_CON_SHIFT); + + return rk3328_saradc_get_clk(cru); +} + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -501,6 +532,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case SCLK_PWM: rate = rk3328_pwm_get_clk(priv->cru); break; + case SCLK_SARADC: + rate = rk3328_saradc_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -531,6 +565,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; + case SCLK_SARADC: + ret = rk3328_saradc_set_clk(priv->cru, rate); + break; default: return -ENOENT; }