| Message ID | 1506773601-27315-3-git-send-email-david.wu@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi David, Am Samstag, 30. September 2017, 20:13:21 CEST schrieb David Wu: > If the gmac-m1 optimization(bit10) is selected, the gpio function > of gmac pins is not valid. We may use the rmii mode for gmac interface, > the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not > used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, > and gmac_rxd0m3 select bit10 is more correct. > > Signed-off-by: David Wu <david.wu@rock-chips.com> the patch subject should mention the the rk3328 whose routing gets fixed (like adding a simple "on rk3328" to it), otherwise Reviewed-by: Heiko Stuebner <heiko@sntech.de>
On Sat, Sep 30, 2017 at 5:07 PM, Heiko Stuebner <heiko@sntech.de> wrote: > Am Samstag, 30. September 2017, 20:13:21 CEST schrieb David Wu: >> If the gmac-m1 optimization(bit10) is selected, the gpio function >> of gmac pins is not valid. We may use the rmii mode for gmac interface, >> the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not >> used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, >> and gmac_rxd0m3 select bit10 is more correct. >> >> Signed-off-by: David Wu <david.wu@rock-chips.com> > > the patch subject should mention the the rk3328 whose routing gets fixed > (like adding a simple "on rk3328" to it), otherwise > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> I added rk3328 to it, also assumed this Reviewed-by covers patch 1/2 as well and applied both with your tag. Yours, Linus Walleij
Hi Linus, Am Samstag, 7. Oktober 2017, 12:32:51 CEST schrieb Linus Walleij: > On Sat, Sep 30, 2017 at 5:07 PM, Heiko Stuebner <heiko@sntech.de> wrote: > > Am Samstag, 30. September 2017, 20:13:21 CEST schrieb David Wu: > >> If the gmac-m1 optimization(bit10) is selected, the gpio function > >> of gmac pins is not valid. We may use the rmii mode for gmac interface, > >> the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not > >> used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, > >> and gmac_rxd0m3 select bit10 is more correct. > >> > >> Signed-off-by: David Wu <david.wu@rock-chips.com> > > > > the patch subject should mention the the rk3328 whose routing gets fixed > > (like adding a simple "on rk3328" to it), otherwise > > > > Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > I added rk3328 to it, also assumed this Reviewed-by covers patch 1/2 > as well and applied both with your tag. while I did mean to cross-check patch 1/2 separately with the soc manual, I got sidetracked with my current vacation :-) . Anyway, it did look ok on first glance then and I also cannot find issues with it now. So all is good. Heiko
Hi Linus, Thanks for you adding it. I left the office for a few days due to holiday. 在 2017/10/7 18:32, Linus Walleij 写道: > On Sat, Sep 30, 2017 at 5:07 PM, Heiko Stuebner <heiko@sntech.de> wrote: >> Am Samstag, 30. September 2017, 20:13:21 CEST schrieb David Wu: >>> If the gmac-m1 optimization(bit10) is selected, the gpio function >>> of gmac pins is not valid. We may use the rmii mode for gmac interface, >>> the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not >>> used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, >>> and gmac_rxd0m3 select bit10 is more correct. >>> >>> Signed-off-by: David Wu <david.wu@rock-chips.com> >> >> the patch subject should mention the the rk3328 whose routing gets fixed >> (like adding a simple "on rk3328" to it), otherwise >> >> Reviewed-by: Heiko Stuebner <heiko@sntech.de> > > I added rk3328 to it, also assumed this Reviewed-by covers patch 1/2 > as well and applied both with your tag. > > Yours, > Linus Walleij > > >
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index c7c9beb..9e0cabf 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -900,12 +900,19 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, .route_offset = 0x50, .route_val = BIT(16) | BIT(16 + 1) | BIT(0), }, { - /* gmac-m1-optimized_rxd0 */ + /* gmac-m1_rxd0 */ .bank_num = 1, .pin = 11, .func = 2, .route_offset = 0x50, - .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10), + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* gmac-m1-optimized_rxd3 */ + .bank_num = 1, + .pin = 14, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 10) | BIT(10), }, { /* pdm_sdi0m0 */ .bank_num = 2,
If the gmac-m1 optimization(bit10) is selected, the gpio function of gmac pins is not valid. We may use the rmii mode for gmac interface, the pins such as rx_d2, rx_d3, which the rgmii mode used, but rmii not used could be taken as gpio function. So gmac_rxd0m1 selects the bit2, and gmac_rxd0m3 select bit10 is more correct. Signed-off-by: David Wu <david.wu@rock-chips.com> --- drivers/pinctrl/pinctrl-rockchip.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)