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Received: from regular1.263xmail.com ([211.150.99.141]) by merlin.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1djzp6-0002Yh-EK; Tue, 22 Aug 2017 03:25:51 +0000 Received: from jeffy.chen?rock-chips.com (unknown [192.168.167.229]) by regular1.263xmail.com (Postfix) with ESMTP id 97FF787; Tue, 22 Aug 2017 11:20:18 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 9D0C03D0; Tue, 22 Aug 2017 11:20:13 +0800 (CST) X-RL-SENDER: jeffy.chen@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: jeffy.chen@rock-chips.com X-UNIQUE-TAG: <241a1be96007866047947579c921111f> X-ATTACHMENT-NUM: 0 X-SENDER: cjf@rock-chips.com X-DNS-TYPE: 0 Received: from localhost (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith ESMTP id 14468OX5VA2; Tue, 22 Aug 2017 11:20:18 +0800 (CST) From: Jeffy Chen To: linux-kernel@vger.kernel.org, bhelgaas@google.com Subject: [PATCH v4 3/4] dt-bindings: PCI: rockchip: Add support for pcie wake irq Date: Tue, 22 Aug 2017 11:19:33 +0800 Message-Id: <20170822031934.8675-4-jeffy.chen@rock-chips.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170822031934.8675-1-jeffy.chen@rock-chips.com> References: <20170822031934.8675-1-jeffy.chen@rock-chips.com> X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Jeffy Chen , Heiko Stuebner , linux-pci@vger.kernel.org, shawn.lin@rock-chips.com, briannorris@chromium.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, Rob Herring , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add an optional interrupt for PCIE_WAKE pin. Signed-off-by: Jeffy Chen --- Changes in v4: None Changes in v3: None Changes in v2: None .../devicetree/bindings/pci/rockchip-pcie.txt | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt index 5678be82530d..9f6504129e80 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt @@ -20,10 +20,13 @@ Required properties: - msi-map: Maps a Requester ID to an MSI controller and associated msi-specifier data. See ./pci-msi.txt - interrupts: Three interrupt entries must be specified. -- interrupt-names: Must include the following names - - "sys" - - "legacy" - - "client" +- interrupt-names: Include the following names + Required: + - "sys" + - "legacy" + - "client" + Optional: + - "wake" - resets: Must contain seven entries for each entry in reset-names. See ../reset/reset.txt for details. - reset-names: Must include the following names @@ -87,10 +90,11 @@ pcie0: pcie@f8000000 { clock-names = "aclk", "aclk-perf", "hclk", "pm"; bus-range = <0x0 0x1>; - interrupts = , - , - ; - interrupt-names = "sys", "legacy", "client"; + interrupts-extended = <&gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, + <&gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, + <&gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>, + <&gpio0 8 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sys", "legacy", "client", "wake"; assigned-clocks = <&cru SCLK_PCIEPHY_REF>; assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; assigned-clock-rates = <100000000>;