From patchwork Mon Feb 19 07:26:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Klaus Goger X-Patchwork-Id: 10227231 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 583E860392 for ; Mon, 19 Feb 2018 07:26:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3FC8B28871 for ; Mon, 19 Feb 2018 07:26:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 348AF28961; Mon, 19 Feb 2018 07:26:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AF4DC28871 for ; Mon, 19 Feb 2018 07:26:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=INH0XmuJACxd2ZEnKaaxnr+JAV02J/+R6wrV4cJuZac=; b=oZX 1ascgvTBnoXas8rkVJiVSxk3G4YxzZAm2ecE32kh9+dXioL+IDvdu41YyoClV71PzOR5igIvEM/75 ipIFxZojyKh+JmjhAab3HHRW6eLcJf5rQHhwHeMMFBL02aMqNpOppYvVgctMYfKV8NjIYC2Q5331A uQcGvwLLjKwvJ7B73/FTYjzvWPGbY8Kbnx1ev+sDRICaSqQDYp9XPNxQuYpXvrGfXy+x9RTgSrOBp 0v4YPiizhMKQHkhe1vPl73TC6gxZAN6ZCIn+DbnDu78PEHJK5wUun872Tj81LWWTJ6Emg8Ivk8pDm ObHhEbK5GcAXIM/Q7Igrc4RcNULym+Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.89 #1 (Red Hat Linux)) id 1enfqZ-0000X4-3v; Mon, 19 Feb 2018 07:26:47 +0000 Received: from vegas.theobroma-systems.com ([144.76.126.164] helo=mail.theobroma-systems.com) by bombadil.infradead.org with esmtps (Exim 4.89 #1 (Red Hat Linux)) id 1enfqW-0000UK-2Q for linux-rockchip@lists.infradead.org; Mon, 19 Feb 2018 07:26:46 +0000 Received: from [86.59.122.178] (port=46470 helo=blau.lan) by mail.theobroma-systems.com with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1enfqG-0008Ob-9q; Mon, 19 Feb 2018 08:26:28 +0100 From: Klaus Goger To: linux-rockchip@lists.infradead.org Subject: [PATCH v2] arm64: dts: rockchip: add OPPs for rk3368-lion Date: Mon, 19 Feb 2018 08:26:26 +0100 Message-Id: <20180219072626.31874-1-klaus.goger@theobroma-systems.com> X-Mailer: git-send-email 2.11.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180218_232644_271736_960F5C30 X-CRM114-Status: UNSURE ( 8.18 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Klaus Goger , linux-kernel@vger.kernel.org, Heiko Stuebner MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds CPU operation points for the RK3368. We only add them to the the RK3368-uQ7 SoM (Lion) because patches for the SoC where reverted in the past. commit 6354a06cbaa8 ("Revert "arm64: dts: rockchip: Add basic cpu frequencies for RK3368"") Signed-off-by: Klaus Goger --- arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi | 80 +++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi index 1315972412df..a0bcf35b1605 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368-lion.dtsi @@ -11,6 +11,70 @@ stdout-path = "serial0:115200n8"; }; + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000 975000 1350000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000 1050000 1350000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000 1150000 1350000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1300000 1300000 1350000>; + turbo-mode; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000 1300000 1350000>; + turbo-mode; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1025000 1025000 1350000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1125000 1125000 1350000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000 1225000 1350000>; + }; + }; + ext_gmac: gmac-clk { compatible = "fixed-clock"; clock-frequency = <125000000>; @@ -105,35 +169,51 @@ }; &cpu_l0 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; &cpu_l1 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; &cpu_l2 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; &cpu_l3 { + clocks = <&cru ARMCLKL>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster1_opp>; }; &cpu_b0 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; &cpu_b1 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; &cpu_b2 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; &cpu_b3 { + clocks = <&cru ARMCLKB>; cpu-supply = <&vdd_cpu>; + operating-points-v2 = <&cluster0_opp>; }; &emmc {