| Message ID | 20181222164249.25620-1-katsuhiro@katsuster.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: rockchip: fix frac settings of GPLL clock for rk3328 | expand |
Hi, Am Samstag, 22. Dezember 2018, 17:42:49 CET schrieb Katsuhiro Suzuki: > This patch fixes settings of GPLL frequency in fractional mode for > rk3328. In this mode, FOUTVCO is calcurated by following formula: > FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24) > > The problem is in FREF * FRAC >> 24 term. This result always lacks > one from target value is specified by rate member. For example first > itme of rk3328_pll_frac_rate originally has > - rate : 1016064000 > - refdiv: 3 > - fbdiv : 127 > - frac : 134217 > - FREF * FBDIV / REFDIV = 1016000000 > - (FREF * FRAC / REFDIV) >> 24 = 63999 > Thus calculated rate is 1016063999. It seems wrong. > > If frac has 134218 (it is increased 1 from original value), second > term is 64000. All other items have same situation. So this patch > adds 1 to frac member in all items of rk3328_pll_frac_rate. > > Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> so while this sounds all quite right to me, I've added some Rockchip people that have clock experience to hopefully get an Ack on the change :-) @Elaine + Finley: does this explanation and the below change look right? Thanks Heiko > --- > drivers/clk/rockchip/clk-rk3328.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c > index faa94adb2a37..65ab5c2f48b0 100644 > --- a/drivers/clk/rockchip/clk-rk3328.c > +++ b/drivers/clk/rockchip/clk-rk3328.c > @@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = { > > static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = { > /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ > - RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), > + RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218), > /* vco = 1016064000 */ > - RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088), > + RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089), > /* vco = 983040000 */ > - RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088), > + RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089), > /* vco = 983040000 */ > - RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088), > + RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089), > /* vco = 860156000 */ > - RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894), > + RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895), > /* vco = 903168000 */ > - RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329), > + RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330), > /* vco = 819200000 */ > { /* sentinel */ }, > }; >
Hi Elaine, Am Montag, 24. Dezember 2018, 08:48:05 CET schrieb zhangqing@rock-chips.com: > Hi: Heiko: > > This explanation and the change is OK. Thanks for Katsuhiro's correction. thanks for your quick confirmation. Can I make this an Acked-by: Elaine Zhang <zhangqing@rock-chips.com> when applying the patch? Thanks Heiko > 张晴 > 福州瑞芯微电子股份有限公司 > Fuzhou Rockchip Electronics Co.,Ltd > 地址：福建省福州市铜盘路软件大道89号软件园A区21号楼 > Add:No.21 Building, A District, No.89 Software Boulevard Fuzhou, Fujian 350003, P.R.China > Tel:+86-0591-83991906-8601 > 邮编：350003 > E-mail:elaine.zhang@rock-chips.com > > From: Heiko Stuebner > Date: 2018-12-24 15:34 > To: Katsuhiro Suzuki; Finley Xiao; Elaine Zhang > CC: linux-rockchip; linux-arm-kernel; linux-kernel > Subject: Re: [PATCH] clk: rockchip: fix frac settings of GPLL clock for rk3328 > Hi, > > Am Samstag, 22. Dezember 2018, 17:42:49 CET schrieb Katsuhiro Suzuki: > > This patch fixes settings of GPLL frequency in fractional mode for > > rk3328. In this mode, FOUTVCO is calcurated by following formula: > > FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24) > > > > The problem is in FREF * FRAC >> 24 term. This result always lacks > > one from target value is specified by rate member. For example first > > itme of rk3328_pll_frac_rate originally has > > - rate : 1016064000 > > - refdiv: 3 > > - fbdiv : 127 > > - frac : 134217 > > - FREF * FBDIV / REFDIV = 1016000000 > > - (FREF * FRAC / REFDIV) >> 24 = 63999 > > Thus calculated rate is 1016063999. It seems wrong. > > > > If frac has 134218 (it is increased 1 from original value), second > > term is 64000. All other items have same situation. So this patch > > adds 1 to frac member in all items of rk3328_pll_frac_rate. > > > > Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> > > so while this sounds all quite right to me, I've added some Rockchip > people that have clock experience to hopefully get an Ack on the > change :-) > > @Elaine + Finley: does this explanation and the below change look right? > > > Thanks > Heiko > > > --- > > drivers/clk/rockchip/clk-rk3328.c | 12 ++++++------ > > 1 file changed, 6 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c > > index faa94adb2a37..65ab5c2f48b0 100644 > > --- a/drivers/clk/rockchip/clk-rk3328.c > > +++ b/drivers/clk/rockchip/clk-rk3328.c > > @@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = { > > > > static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = { > > /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ > > - RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), > > + RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218), > > /* vco = 1016064000 */ > > - RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088), > > + RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089), > > /* vco = 983040000 */ > > - RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088), > > + RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089), > > /* vco = 983040000 */ > > - RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088), > > + RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089), > > /* vco = 860156000 */ > > - RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894), > > + RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895), > > /* vco = 903168000 */ > > - RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329), > > + RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330), > > /* vco = 819200000 */ > > { /* sentinel */ }, > > }; > > > > > > > >
Am Samstag, 22. Dezember 2018, 17:42:49 CET schrieb Katsuhiro Suzuki: > This patch fixes settings of GPLL frequency in fractional mode for > rk3328. In this mode, FOUTVCO is calcurated by following formula: > FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24) > > The problem is in FREF * FRAC >> 24 term. This result always lacks > one from target value is specified by rate member. For example first > itme of rk3328_pll_frac_rate originally has > - rate : 1016064000 > - refdiv: 3 > - fbdiv : 127 > - frac : 134217 > - FREF * FBDIV / REFDIV = 1016000000 > - (FREF * FRAC / REFDIV) >> 24 = 63999 > Thus calculated rate is 1016063999. It seems wrong. > > If frac has 134218 (it is increased 1 from original value), second > term is 64000. All other items have same situation. So this patch > adds 1 to frac member in all items of rk3328_pll_frac_rate. > > Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> applied for 4.22 with Elaine's Acked-by Thanks Heiko
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index faa94adb2a37..65ab5c2f48b0 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = { static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = { /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ - RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), + RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218), /* vco = 1016064000 */ - RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088), + RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089), /* vco = 983040000 */ - RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088), + RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089), /* vco = 983040000 */ - RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088), + RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089), /* vco = 860156000 */ - RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894), + RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895), /* vco = 903168000 */ - RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329), + RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330), /* vco = 819200000 */ { /* sentinel */ }, };
This patch fixes settings of GPLL frequency in fractional mode for rk3328. In this mode, FOUTVCO is calcurated by following formula: FOUTVCO = FREF * FBDIV / REFDIV + ((FREF * FRAC / REFDIV) >> 24) The problem is in FREF * FRAC >> 24 term. This result always lacks one from target value is specified by rate member. For example first itme of rk3328_pll_frac_rate originally has - rate : 1016064000 - refdiv: 3 - fbdiv : 127 - frac : 134217 - FREF * FBDIV / REFDIV = 1016000000 - (FREF * FRAC / REFDIV) >> 24 = 63999 Thus calculated rate is 1016063999. It seems wrong. If frac has 134218 (it is increased 1 from original value), second term is 64000. All other items have same situation. So this patch adds 1 to frac member in all items of rk3328_pll_frac_rate. Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> --- drivers/clk/rockchip/clk-rk3328.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)