| Message ID | 20190328171710.31949-7-dianders@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/panel: simple: Add mode support to devicetree | expand |
Am Donnerstag, 28. März 2019, 18:17:09 CET schrieb Douglas Anderson: > Let's document the display timings that jerry has been using out in > the field. This uses the standard blankings but a slightly slower > clock rate, thus getting a refresh rate 58.3 Hz. > > NOTE: this won't really do anything except cause DRM to properly > report the refresh rate since vop_crtc_mode_fixup() was rounding the > pixel clock to 74.25 MHz anyway. Apparently the adjusted rate isn't > exposed to userspace so it's important that the rate we're trying to > achieve is mostly right. > > For the downstream kernel change related to this see See > https://crrev.com/c/324558. > > NOTE: minnie will be fixed up in a future patch, so for now we'll just > delete the panel timings there. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- > > Changes in v4: > - rk3288-veyron-jerry patch new for v4. > > Changes in v3: None > Changes in v2: None > > arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 14 ++++++++++++++ hmm, the commit message explicitly mentions jerry, but this is the general panel definition for most veyron-chromebooks (jerry, pinky, jaq,...)? It does work on both pinky and jerry for me, so I guess just the commit message needs a bit adapting? Heiko
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index b54746df3661..0b1789b50c21 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -76,6 +76,20 @@ power-supply = <&vcc33_lcd>; backlight = <&backlight>; + panel-timing { + clock-frequency = <74250000>; + hactive = <1366>; + hfront-porch = <136>; + hback-porch = <60>; + hsync-len = <30>; + hsync-active = <0>; + vactive = <768>; + vfront-porch = <8>; + vback-porch = <12>; + vsync-len = <12>; + vsync-active = <0>; + }; + ports { panel_in: port { panel_in_edp: endpoint { diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index f95d0c5fcf71..ca7512ade222 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -142,6 +142,8 @@ &panel { compatible = "auo,b101ean01", "simple-panel"; power-supply= <&panel_regulator>; + + /delete-node/ panel-timing; }; &rk808 {
Let's document the display timings that jerry has been using out in the field. This uses the standard blankings but a slightly slower clock rate, thus getting a refresh rate 58.3 Hz. NOTE: this won't really do anything except cause DRM to properly report the refresh rate since vop_crtc_mode_fixup() was rounding the pixel clock to 74.25 MHz anyway. Apparently the adjusted rate isn't exposed to userspace so it's important that the rate we're trying to achieve is mostly right. For the downstream kernel change related to this see See https://crrev.com/c/324558. NOTE: minnie will be fixed up in a future patch, so for now we'll just delete the panel timings there. Signed-off-by: Douglas Anderson <dianders@chromium.org> --- Changes in v4: - rk3288-veyron-jerry patch new for v4. Changes in v3: None Changes in v2: None arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi | 14 ++++++++++++++ arch/arm/boot/dts/rk3288-veyron-minnie.dts | 2 ++ 2 files changed, 16 insertions(+)