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b=Gc2otwbY1yPnbbnjiF4paZdZDU6a/hHn+p9tiTxFiVegXhGYJJCOAnn7LmuvB7RpO5 1tW9EKE25ERebGjlzG8s0xvQOhu5HMVyUNaNYY4dbYY5Rbz29yKXEKrUbXWHjn6WNwI4 YRaBd6P4UkKtYfS/X5AwzxZUMrQyX5e/xb0lIszXfte4FMSk6wC06tOGKc/wy5sLbvpl ZikYjPCKf7LPOuCMDakDTt5llVb8bCtEBTBeCVDmACQLv6L7HUJ0ngCweRX4f0M9Zj/e SRQFhGLFWPCOGAd7kFhpHe2nx0sZMD6nOm1o9yHYoKRSyICFwkE87CVyyURPdahViTjo QxRA== X-Gm-Message-State: APjAAAUTXEdHTcmRNOq5lOVJ5NCryo9kc11nh6qJzs+qPkR0akjQgaDW rUqZfiw+G7B4kAZIfpsVx9XWiA== X-Google-Smtp-Source: APXvYqwD4Qo3e9qUi57ZVQh4GPpV+TC78quohbp4D0Vaxq2cmqU8sakD0iIm4mwYRaEvoGRpOT4Bfg== X-Received: by 2002:a17:902:b20f:: with SMTP id t15mr6301266plr.341.1555712322413; Fri, 19 Apr 2019 15:18:42 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:202:1:24fa:e766:52c9:e3b2]) by smtp.gmail.com with ESMTPSA id a3sm8162536pfn.182.2019.04.19.15.18.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Apr 2019 15:18:41 -0700 (PDT) From: Douglas Anderson To: Russell King Subject: [PATCH 2/2] ARM: errata: add support for A12/A17 errata CR711784 Date: Fri, 19 Apr 2019 15:18:03 -0700 Message-Id: <20190419221803.99322-2-dianders@chromium.org> X-Mailer: git-send-email 2.21.0.593.g511ec345e18-goog In-Reply-To: <20190419221803.99322-1-dianders@chromium.org> References: <20190419221803.99322-1-dianders@chromium.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190419_151843_226771_9C192B54 X-CRM114-Status: GOOD ( 13.69 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Florian Fainelli , Salva.Climent@arm.com, Arnd Bergmann , Masahiro Yamada , Marc Zyngier , robin.murphy@arm.com, Tony Lindgren , Palmer Dabbelt , will.deacon@arm.com, bbatacha@arm.com, Douglas Anderson , Ard Biesheuvel , linux-rockchip@lists.infradead.org, Paul Burton , mka@chromium.org, Geert Uytterhoeven , linux-arm-kernel@lists.infradead.org, sonnyrao@chromium.org, linux-kernel@vger.kernel.org, heiko@sntech.de Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds a code for turning on chicken bit 11, which appears to avoid a potential CPU deadlock that could occur. The exact set of instruction needed to trigger this errata is not totaly known but we have a high level of confidence that the problem is fixed by setting chicken bit 11. All details are in http://crbug.com/711784 This erratum has no known number and thus I have tagged it CR711784 (after the Chrome OS bug number). I have created separate A12 / A17 configs to match how the rest of the A12 / A17 errata is handled. Signed-off-by: Douglas Anderson --- arch/arm/Kconfig | 18 ++++++++++++++++++ arch/arm/mm/proc-v7.S | 10 ++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4376fe74f95e..34ec9039206b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1181,6 +1181,13 @@ config ARM_ERRATA_857271 hang. The workaround is expected to have a negligible performance impact. +config ARM_ERRATA_CR711784_A12 + bool "ARM errata: A12: conditional instructions can lead to a CPU hang" + depends on CPU_V7 + help + This option enables the workaround for a Cortex-A12 erratum without a + number. The problems are best described in https://crbug.com/711784 + config ARM_ERRATA_852421 bool "ARM errata: A17: DMB ST might fail to create order between stores" depends on CPU_V7 @@ -1212,6 +1219,17 @@ config ARM_ERRATA_857272 config option from the A12 erratum due to the way errata are checked for and handled. +config ARM_ERRATA_CR711784_A17 + bool "ARM errata: A17: conditional instructions can lead to a CPU hang" + depends on CPU_V7 + help + This option enables the workaround for a Cortex-A17 erratum without a + number. The problems are best described in https://crbug.com/711784 + This erratum is not known to be fixed in any A17 revision. + This is identical to Cortex-A12 erratum CR711784. It is a separate + config option from the A12 erratum due to the way errata are checked + for and handled. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index cd2accbab844..a5156ea734ee 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -396,6 +396,11 @@ __ca12_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 10 @ set bit #10 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_CR711784_A12 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 11 @ set bit #11 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish @@ -416,6 +421,11 @@ __ca17_errata: mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register orr r10, r10, #1 << 10 @ set bit #10 mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif +#ifdef CONFIG_ARM_ERRATA_CR711784_A17 + mrc p15, 0, r10, c15, c0, 1 @ read diagnostic register + orr r10, r10, #1 << 11 @ set bit #11 + mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif b __errata_finish