From patchwork Wed Nov 6 11:26:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Heiko Stuebner X-Patchwork-Id: 11230043 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A49A616B1 for ; Wed, 6 Nov 2019 11:27:52 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7063D20659 for ; Wed, 6 Nov 2019 11:27:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lHhJH5Wq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7063D20659 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=theobroma-systems.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ERp//T8KEvzHqb8Ge6fpxMzsogScTUKnxQ8RR+P7dHc=; b=lHhJH5Wqx133jn e97eqUmy1d/CtUNIeSYtYcuMNaBqkFqUzP2bts0c7FG1PDHMGJOgiO1mnQRM8s7FOyY9mxzLrsA33 6UkK02i24WcVX5d/yHhNlZzea8JBjTpRho2cW9RsFL+Zvhq4txGCwUV1IRRkbi+dmC0PwveSOZPE2 AxPHckmBAPFN6NEBX13j/9xtejWqivT+ByuyRfFVhHVPWFK44ARigaU+Muf7xCsPK9UrsQ67JE1oz ThpLGDoJG1rkTVs0C3i3HyUfjAvkrhVNUtKZYhA/6mPD8puOlo6XyO6ZadbK/f03IODdwRD1sIcrd Oj738FaPav5/1n9C5j0Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iSJTY-0003cu-JA; Wed, 06 Nov 2019 11:27:48 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iSJT8-0003BF-3k; Wed, 06 Nov 2019 11:27:23 +0000 Received: from [94.134.91.181] (helo=phil.fritz.box) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.89) (envelope-from ) id 1iSJSn-0004nK-UE; Wed, 06 Nov 2019 12:27:02 +0100 From: Heiko Stuebner To: dri-devel@lists.freedesktop.org, a.hajda@samsung.com Subject: [PATCH 2/3] drm/rockchip: add ability to handle external dphys in mipi-dsi Date: Wed, 6 Nov 2019 12:26:49 +0100 Message-Id: <20191106112650.8365-2-heiko.stuebner@theobroma-systems.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191106112650.8365-1-heiko.stuebner@theobroma-systems.com> References: <20191106112650.8365-1-heiko.stuebner@theobroma-systems.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191106_032722_306297_B889825B X-CRM114-Status: GOOD ( 18.64 ) X-Spam-Score: 0.7 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.7 SPF_NEUTRAL SPF: sender does not match SPF record (neutral) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, jernej.skrabec@siol.net, heiko@sntech.de, jonas@kwiboo.se, linux-kernel@vger.kernel.org, narmstrong@baylibre.com, hjc@rock-chips.com, philippe.cornu@st.com, yannick.fertre@st.com, linux-rockchip@lists.infradead.org, robh+dt@kernel.org, Laurent.pinchart@ideasonboard.com, Heiko Stuebner , linux-arm-kernel@lists.infradead.org, christoph.muellner@theobroma-systems.com Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org While the common case is that the dsi controller uses an internal dphy, accessed through the phy registers inside the dsi controller, there is also the possibility to use a separate dphy from a different vendor. One such case is the Rockchip px30 that uses a Innosilicon Mipi dphy, so add the support for handling such a constellation, including the pll also getting generated inside that external phy. Signed-off-by: Heiko Stuebner --- .../display/rockchip/dw_mipi_dsi_rockchip.txt | 7 ++- .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 54 ++++++++++++++++++- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index ce4c1fc9116c..8b25156a9dcf 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -8,8 +8,9 @@ Required properties: "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi". - reg: Represent the physical address range of the controller. - interrupts: Represent the controller's interrupt to the CPU(s). -- clocks, clock-names: Phandles to the controller's pll reference - clock(ref) and APB clock(pclk). For RK3399, a phy config clock +- clocks, clock-names: Phandles to the controller's and APB clock(pclk) + and either a pll reference clock(ref) (internal dphy) or pll clock(pll) + (when connected to an external phy). For RK3399, a phy config clock (phy_cfg) and a grf clock(grf) are required. As described in [1]. - rockchip,grf: this soc should set GRF regs to mux vopl/vopb. - ports: contain a port node with endpoint definitions as defined in [2]. @@ -18,6 +19,8 @@ Required properties: - video port 1 for either a panel or subsequent encoder Optional properties: +- phys: from general PHY binding: the phandle for the PHY device. +- phy-names: Should be "dphy" if phys references an external phy. - power-domains: a phandle to mipi dsi power domain node. - resets: list of phandle + reset specifier pairs, as described in [3]. - reset-names: string reset name, must be "apb". diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index bc073ec5c183..99ec625e0448 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -223,6 +224,9 @@ struct dw_mipi_dsi_rockchip { bool is_slave; struct dw_mipi_dsi_rockchip *slave; + /* optional external dphy */ + struct phy *phy; + unsigned int lane_mbps; /* per lane */ u16 input_div; u16 feedback_div; @@ -359,6 +363,9 @@ static int dw_mipi_dsi_phy_init(void *priv_data) struct dw_mipi_dsi_rockchip *dsi = priv_data; int ret, i, vco; + if (dsi->phy) + return 0; + /* * Get vco from frequency(lane_mbps) * vco frequency table @@ -467,6 +474,27 @@ static int dw_mipi_dsi_phy_init(void *priv_data) return ret; } +static void dw_mipi_dsi_phy_power_on(void *priv_data) +{ + struct dw_mipi_dsi_rockchip *dsi = priv_data; + int ret; + + ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); + if (ret) { + DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); + return; + } + + phy_power_on(dsi->phy); +} + +static void dw_mipi_dsi_phy_power_off(void *priv_data) +{ + struct dw_mipi_dsi_rockchip *dsi = priv_data; + + phy_power_off(dsi->phy); +} + static int dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, unsigned long mode_flags, u32 lanes, u32 format, @@ -504,9 +532,21 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, "DPHY clock frequency is out of range\n"); } - fin = clk_get_rate(dsi->pllref_clk); fout = target_mbps * USEC_PER_SEC; + /* an external phy does have a controllable pll clk */ + if (dsi->phy) { + fout = clk_round_rate(dsi->pllref_clk, fout); + clk_set_rate(dsi->pllref_clk, fout); + + dsi->lane_mbps = target_mbps; + *lane_mbps = dsi->lane_mbps; + + return 0; + } + + fin = clk_get_rate(dsi->pllref_clk); + /* constraint: 5Mhz <= Fref / N <= 40MHz */ min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); max_prediv = fin / (5 * USEC_PER_SEC); @@ -561,6 +601,8 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { .init = dw_mipi_dsi_phy_init, + .power_on = dw_mipi_dsi_phy_power_on, + .power_off = dw_mipi_dsi_phy_power_off, .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, }; @@ -920,7 +962,15 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) return -EINVAL; } - dsi->pllref_clk = devm_clk_get(dev, "ref"); + /* try to get a possible external dphy */ + dsi->phy = devm_phy_optional_get(dev, "dphy"); + if (IS_ERR(dsi->phy)) { + ret = PTR_ERR(dsi->phy); + DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); + return ret; + } + + dsi->pllref_clk = devm_clk_get(dev, dsi->phy ? "pll" : "ref"); if (IS_ERR(dsi->pllref_clk)) { ret = PTR_ERR(dsi->pllref_clk); DRM_DEV_ERROR(dev,