| Message ID | 20200303192956.64410-1-jbrunet@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | clk: rockchip: fix mmc get phase | expand |
Quoting Jerome Brunet (2020-03-03 11:29:56) > If the mmc clock has no rate, it can be assumed to be constant. > In such case, there is no measurable phase shift. Just return 0 > in this case instead of returning an error. > > Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk > registration") > Tested-by: Markus Reichl <m.reichl@fivetechno.de> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > --- Applied to clk-next right on top of the phase branch.
diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c index 4abe7ff31f53..975454a3dd72 100644 --- a/drivers/clk/rockchip/clk-mmc-phase.c +++ b/drivers/clk/rockchip/clk-mmc-phase.c @@ -51,9 +51,9 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw) u16 degrees; u32 delay_num = 0; - /* See the comment for rockchip_mmc_set_phase below */ + /* Constant signal, no measurable phase shift */ if (!rate) - return -EINVAL; + return 0; raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
If the mmc clock has no rate, it can be assumed to be constant. In such case, there is no measurable phase shift. Just return 0 in this case instead of returning an error. Fixes: 2760878662a2 ("clk: Bail out when calculating phase fails during clk registration") Tested-by: Markus Reichl <m.reichl@fivetechno.de> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- drivers/clk/rockchip/clk-mmc-phase.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)