From patchwork Fri Jul 17 03:23:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668895 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AD4C014E3 for ; Fri, 17 Jul 2020 03:24:34 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8192421702 for ; Fri, 17 Jul 2020 03:24:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FGFoJeO/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8192421702 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AEFenF95REyPzBySKAR0f+zv2l1eXtlcWV/5UXE1zxM=; b=FGFoJeO/sIwjeAsm+xnNvNZUaC xa1uWuMw2hy+XG8SYy/Q3spUIlBRpGMTWTKnxEQr2IvJGtck6crwVhyBHrBphIgrTg77wvAg39EGu 4DP8mbG+S0gUcbLOMYXHmqB1Bo2cpcqxcSx2PcF4oSriHbtG2UQf6Y8NeI1A54al8Sj1TF0rLjrH7 sY4bGFsxVbY5ilxnlR1VI6sLDqcmj+XB06QBHsTmQB0hKfwgwPRcqo5N6RJLiGvuMQOBBTjGU9crZ aLP5/HZXv3fPazYIB2tj8avMzs4WGBUoQplYo9L/czwKB2ZwEjuE3Te/TpAtnFJUKTNucEFpkuTe3 /NXo4NVQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwGz7-0001qM-37; Fri, 17 Jul 2020 03:24:29 +0000 Received: from lucky1.263xmail.com ([211.157.147.133]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwGz2-0001ns-JJ for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 03:24:27 +0000 Received: from localhost (unknown [192.168.167.16]) by lucky1.263xmail.com (Postfix) with ESMTP id A867EC5D61; Fri, 17 Jul 2020 11:24:18 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P18585T140685189564160S1594956256233933_; Fri, 17 Jul 2020 11:24:19 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl Date: Fri, 17 Jul 2020 11:23:59 +0800 Message-Id: <20200717032411.17654-2-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com> References: <20200717032411.17654-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_232425_166291_BA4482DE X-CRM114-Status: UNSURE ( 9.96 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.133 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.133 listed in wl.mailspike.net] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during driver probe. This patch is prepare work for making rockchip_pin_ctrl to be const type. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index c07324d1f265..bc465da68f26 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; + u32 nr_pins; match = of_match_node(rockchip_pinctrl_dt_match, node); ctrl = (struct rockchip_pin_ctrl *)match->data; @@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( drv_pmu_offs = ctrl->pmu_drv_offset; drv_grf_offs = ctrl->grf_drv_offset; bank = ctrl->pin_banks; + nr_pins = 0; for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; raw_spin_lock_init(&bank->slock); bank->drvdata = d; - bank->pin_base = ctrl->nr_pins; - ctrl->nr_pins += bank->nr_pins; + bank->pin_base = nr_pins; + nr_pins += bank->nr_pins; /* calculate iomux and drv offsets */ for (j = 0; j < 4; j++) { @@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( } } + WARN_ON(nr_pins != ctrl->nr_pins); + return ctrl; } @@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = { static struct rockchip_pin_ctrl px30_pin_ctrl = { .pin_banks = px30_pin_banks, .nr_banks = ARRAY_SIZE(px30_pin_banks), + .nr_pins = 128, .label = "PX30-GPIO", .type = PX30, .grf_mux_offset = 0x0, @@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { static struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), + .nr_pins = 128, .label = "RV1108-GPIO", .type = RV1108, .grf_mux_offset = 0x10, @@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = { static struct rockchip_pin_ctrl rk2928_pin_ctrl = { .pin_banks = rk2928_pin_banks, .nr_banks = ARRAY_SIZE(rk2928_pin_banks), + .nr_pins = 128, .label = "RK2928-GPIO", .type = RK2928, .grf_mux_offset = 0xa8, @@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { static struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), + .nr_pins = 96, .label = "RK3036-GPIO", .type = RK2928, .grf_mux_offset = 0xa8, @@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = { static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { .pin_banks = rk3066a_pin_banks, .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), + .nr_pins = 176, .label = "RK3066a-GPIO", .type = RK2928, .grf_mux_offset = 0xa8, @@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = { static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { .pin_banks = rk3066b_pin_banks, .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), + .nr_pins = 128, .label = "RK3066b-GPIO", .type = RK3066B, .grf_mux_offset = 0x60, @@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { static struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), + .nr_pins = 128, .label = "RK3128-GPIO", .type = RK3128, .grf_mux_offset = 0xa8, @@ -3981,6 +3992,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { static struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), + .nr_pins = 128, .label = "RK3188-GPIO", .type = RK3188, .grf_mux_offset = 0x60, @@ -3999,6 +4011,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), + .nr_pins = 128, .label = "RK3228-GPIO", .type = RK3288, .grf_mux_offset = 0x0, @@ -4043,6 +4056,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { static struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), + .nr_pins = 264, .label = "RK3288-GPIO", .type = RK3288, .grf_mux_offset = 0x0, @@ -4079,6 +4093,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = { static struct rockchip_pin_ctrl rk3308_pin_ctrl = { .pin_banks = rk3308_pin_banks, .nr_banks = ARRAY_SIZE(rk3308_pin_banks), + .nr_pins = 160, .label = "RK3308-GPIO", .type = RK3308, .grf_mux_offset = 0x0, @@ -4108,6 +4123,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .nr_pins = 128, .label = "RK3328-GPIO", .type = RK3288, .grf_mux_offset = 0x0, @@ -4134,6 +4150,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { static struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), + .nr_pins = 128, .label = "RK3368-GPIO", .type = RK3368, .grf_mux_offset = 0x0, @@ -4198,6 +4215,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), + .nr_pins = 160, .label = "RK3399-GPIO", .type = RK3399, .grf_mux_offset = 0xe000,