From patchwork Fri Jul 17 03:24:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianqun Xu X-Patchwork-Id: 11668889 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 26FAC159A for ; Fri, 17 Jul 2020 03:24:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC7F921741 for ; Fri, 17 Jul 2020 03:24:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="KLBytLf/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC7F921741 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bF0DUDUbmEcWZtshGj71T7tSeAx8wImphkVmXcOw92M=; b=KLBytLf/O0TyxYW7F9G3rY+KLb 1FLoUIfdpIe1k/i2RPvB1s90JwpFSIskQ74ecs8k642Pw+gi5bds0izfzXeb88okHovJSrZaCDuXb 4OHQ3A43npTdI3ltv499v2/OK7h1b3A0fDu1w6rInXYQn9FbDiwm3Eej9nFYeusDB5o9w7qWc3V/A AoC3qa5UTfCU4Gq1RBATDILehV3SQfIScgMKHXnhHfN8k9GnRQy2N+MrV3zepMFwU/NSAZdVPHX5O +ECyUZOTGVozKBGDTA2I/FYEbWQUyYFhE5eT/1MXMPuw+DQtIGXsgeEdNBMh4+MyfBt4V6Esb3iLv Zu5uFF/A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwGz7-0001qu-W8; Fri, 17 Jul 2020 03:24:30 +0000 Received: from lucky1.263xmail.com ([211.157.147.132]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1jwGz2-0001oH-LL for linux-rockchip@lists.infradead.org; Fri, 17 Jul 2020 03:24:27 +0000 Received: from localhost (unknown [192.168.167.16]) by lucky1.263xmail.com (Postfix) with ESMTP id 81257EC3CC; Fri, 17 Jul 2020 11:24:20 +0800 (CST) X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-ADDR-CHECKED4: 1 X-ANTISPAM-LEVEL: 2 X-ABS-CHECKED: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (postfix) whith ESMTP id P18585T140685189564160S1594956256233933_; Fri, 17 Jul 2020 11:24:20 +0800 (CST) X-IP-DOMAINF: 1 X-UNIQUE-TAG: <287a0cebf96cbfc259e668a351d16120> X-RL-SENDER: jay.xu@rock-chips.com X-SENDER: xjq@rock-chips.com X-LOGIN-NAME: jay.xu@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 X-System-Flag: 0 From: Jianqun Xu To: heiko@sntech.de, linus.walleij@linaro.org Subject: [PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct Date: Fri, 17 Jul 2020 11:24:00 +0800 Message-Id: <20200717032411.17654-3-jay.xu@rock-chips.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200717032411.17654-1-jay.xu@rock-chips.com> References: <20200717032411.17654-1-jay.xu@rock-chips.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200716_232425_238537_E3979D21 X-CRM114-Status: GOOD ( 12.83 ) X-Spam-Score: 1.5 (+) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (1.5 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [211.157.147.132 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [211.157.147.132 listed in wl.mailspike.net] 1.5 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror) 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rockchip@lists.infradead.org, kever.yang@rock-chips.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, david.wu@rock-chips.com, Jianqun Xu MIME-Version: 1.0 Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+patchwork-linux-rockchip=patchwork.kernel.org@lists.infradead.org The rockchip_pin_ctrl structure actually is soc data structure for pinctrl on Rockchip SoCs. Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 62 +++++++++++++++--------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index bc465da68f26..77c1e6744f6c 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -392,7 +392,7 @@ struct rockchip_pinctrl { struct regmap *regmap_pull; struct regmap *regmap_pmu; struct device *dev; - struct rockchip_pin_ctrl *ctrl; + const struct rockchip_pin_ctrl *ctrl; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; struct rockchip_pin_group *groups; @@ -779,7 +779,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_mux_recalced_data *data; int i; @@ -1396,7 +1396,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, int mux, u32 *loc, u32 *reg, u32 *value) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_mux_route_data *data; int i; @@ -2112,7 +2112,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u32 data, temp, rmask_bits; @@ -2189,7 +2189,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, int pin_num, int strength) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret, i; u32 data, rmask, rmask_bits, temp; @@ -2297,7 +2297,7 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = { static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret, pull_type; u8 bit; @@ -2341,7 +2341,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, int pin_num, int pull) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret, i, pull_type; u8 bit; @@ -2427,7 +2427,7 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u8 bit; @@ -2449,7 +2449,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, int pin_num, int enable) { struct rockchip_pinctrl *info = bank->drvdata; - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct regmap *regmap; int reg, ret; u8 bit; @@ -2621,7 +2621,7 @@ static const struct pinmux_ops rockchip_pmx_ops = { * Pinconf_ops handling */ -static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, +static bool rockchip_pinconf_pull_valid(const struct rockchip_pin_ctrl *ctrl, enum pin_config_param pull) { switch (ctrl->type) { @@ -3366,7 +3366,7 @@ static void rockchip_irq_disable(struct irq_data *d) static int rockchip_interrupts_register(struct platform_device *pdev, struct rockchip_pinctrl *info) { - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; struct irq_chip_generic *gc; @@ -3447,7 +3447,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev, static int rockchip_gpiolib_register(struct platform_device *pdev, struct rockchip_pinctrl *info) { - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; struct gpio_chip *gc; int ret; @@ -3493,7 +3493,7 @@ static int rockchip_gpiolib_register(struct platform_device *pdev, static int rockchip_gpiolib_unregister(struct platform_device *pdev, struct rockchip_pinctrl *info) { - struct rockchip_pin_ctrl *ctrl = info->ctrl; + const struct rockchip_pin_ctrl *ctrl = info->ctrl; struct rockchip_pin_bank *bank = ctrl->pin_banks; int i; @@ -3563,20 +3563,20 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, static const struct of_device_id rockchip_pinctrl_dt_match[]; /* retrieve the soc specific data */ -static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( +static const struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( struct rockchip_pinctrl *d, struct platform_device *pdev) { const struct of_device_id *match; struct device_node *node = pdev->dev.of_node; struct device_node *np; - struct rockchip_pin_ctrl *ctrl; + const const struct rockchip_pin_ctrl *ctrl; struct rockchip_pin_bank *bank; int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; u32 nr_pins; match = of_match_node(rockchip_pinctrl_dt_match, node); - ctrl = (struct rockchip_pin_ctrl *)match->data; + ctrl = (const struct rockchip_pin_ctrl *)match->data; for_each_child_of_node(node, np) { if (!of_find_property(np, "gpio-controller", NULL)) @@ -3748,7 +3748,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) { struct rockchip_pinctrl *info; struct device *dev = &pdev->dev; - struct rockchip_pin_ctrl *ctrl; + const const struct rockchip_pin_ctrl *ctrl; struct device_node *np = pdev->dev.of_node, *node; struct resource *res; void __iomem *base; @@ -3853,7 +3853,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = { ), }; -static struct rockchip_pin_ctrl px30_pin_ctrl = { +static const struct rockchip_pin_ctrl px30_pin_ctrl = { .pin_banks = px30_pin_banks, .nr_banks = ARRAY_SIZE(px30_pin_banks), .nr_pins = 128, @@ -3878,7 +3878,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = { PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), }; -static struct rockchip_pin_ctrl rv1108_pin_ctrl = { +static const struct rockchip_pin_ctrl rv1108_pin_ctrl = { .pin_banks = rv1108_pin_banks, .nr_banks = ARRAY_SIZE(rv1108_pin_banks), .nr_pins = 128, @@ -3900,7 +3900,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk2928_pin_ctrl = { +static const struct rockchip_pin_ctrl rk2928_pin_ctrl = { .pin_banks = rk2928_pin_banks, .nr_banks = ARRAY_SIZE(rk2928_pin_banks), .nr_pins = 128, @@ -3916,7 +3916,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = { PIN_BANK(2, 32, "gpio2"), }; -static struct rockchip_pin_ctrl rk3036_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3036_pin_ctrl = { .pin_banks = rk3036_pin_banks, .nr_banks = ARRAY_SIZE(rk3036_pin_banks), .nr_pins = 96, @@ -3935,7 +3935,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = { PIN_BANK(6, 16, "gpio6"), }; -static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = { .pin_banks = rk3066a_pin_banks, .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), .nr_pins = 176, @@ -3952,7 +3952,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = { .pin_banks = rk3066b_pin_banks, .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), .nr_pins = 128, @@ -3968,7 +3968,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3128_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3128_pin_ctrl = { .pin_banks = rk3128_pin_banks, .nr_banks = ARRAY_SIZE(rk3128_pin_banks), .nr_pins = 128, @@ -3989,7 +3989,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3188_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3188_pin_ctrl = { .pin_banks = rk3188_pin_banks, .nr_banks = ARRAY_SIZE(rk3188_pin_banks), .nr_pins = 128, @@ -4008,7 +4008,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3228_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3228_pin_ctrl = { .pin_banks = rk3228_pin_banks, .nr_banks = ARRAY_SIZE(rk3228_pin_banks), .nr_pins = 128, @@ -4053,7 +4053,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = { PIN_BANK(8, 16, "gpio8"), }; -static struct rockchip_pin_ctrl rk3288_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3288_pin_ctrl = { .pin_banks = rk3288_pin_banks, .nr_banks = ARRAY_SIZE(rk3288_pin_banks), .nr_pins = 264, @@ -4090,7 +4090,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = { IOMUX_WIDTH_2BIT), }; -static struct rockchip_pin_ctrl rk3308_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3308_pin_ctrl = { .pin_banks = rk3308_pin_banks, .nr_banks = ARRAY_SIZE(rk3308_pin_banks), .nr_pins = 160, @@ -4120,7 +4120,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { 0), }; -static struct rockchip_pin_ctrl rk3328_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3328_pin_ctrl = { .pin_banks = rk3328_pin_banks, .nr_banks = ARRAY_SIZE(rk3328_pin_banks), .nr_pins = 128, @@ -4147,7 +4147,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = { PIN_BANK(3, 32, "gpio3"), }; -static struct rockchip_pin_ctrl rk3368_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3368_pin_ctrl = { .pin_banks = rk3368_pin_banks, .nr_banks = ARRAY_SIZE(rk3368_pin_banks), .nr_pins = 128, @@ -4212,7 +4212,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = { ), }; -static struct rockchip_pin_ctrl rk3399_pin_ctrl = { +static const struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pin_banks = rk3399_pin_banks, .nr_banks = ARRAY_SIZE(rk3399_pin_banks), .nr_pins = 160,