@@ -202,34 +202,6 @@ config PCI_HOST_THUNDER_ECAM
help
Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
-config PCIE_ROCKCHIP
- bool
- depends on PCI
-
-config PCIE_ROCKCHIP_HOST
- tristate "Rockchip PCIe host controller"
- depends on ARCH_ROCKCHIP || COMPILE_TEST
- depends on OF
- depends on PCI_MSI_IRQ_DOMAIN
- select MFD_SYSCON
- select PCIE_ROCKCHIP
- help
- Say Y here if you want internal PCI support on Rockchip SoC.
- There is 1 internal PCIe port available to support GEN2 with
- 4 slots.
-
-config PCIE_ROCKCHIP_EP
- bool "Rockchip PCIe endpoint controller"
- depends on ARCH_ROCKCHIP || COMPILE_TEST
- depends on OF
- depends on PCI_ENDPOINT
- select MFD_SYSCON
- select PCIE_ROCKCHIP
- help
- Say Y here if you want to support Rockchip PCIe controller in
- endpoint mode on Rockchip SoC. There is 1 internal PCIe port
- available to support GEN2 with 4 slots.
-
config PCIE_MEDIATEK
tristate "MediaTek PCIe controller"
depends on ARCH_MEDIATEK || COMPILE_TEST
@@ -23,9 +23,6 @@ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
-obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
-obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
-obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
@@ -65,4 +65,32 @@ config PCI_J721E_EP
Say Y here if you want to support the TI J721E PCIe platform
controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe
core.
+
+config PCIE_ROCKCHIP
+ bool
+
+config PCIE_ROCKCHIP_HOST
+ tristate "Rockchip PCIe host controller"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on OF
+ depends on PCI_MSI_IRQ_DOMAIN
+ select MFD_SYSCON
+ select PCIE_ROCKCHIP
+ help
+ Say Y here if you want internal PCI support on Rockchip SoC.
+ There is 1 internal PCIe port available to support GEN2 with
+ 4 slots.
+
+config PCIE_ROCKCHIP_EP
+ bool "Rockchip PCIe endpoint controller"
+ depends on ARCH_ROCKCHIP || COMPILE_TEST
+ depends on OF
+ depends on PCI_ENDPOINT
+ select MFD_SYSCON
+ select PCIE_ROCKCHIP
+ help
+ Say Y here if you want to support Rockchip PCIe controller in
+ endpoint mode on Rockchip SoC. There is 1 internal PCIe port
+ available to support GEN2 with 4 slots.
+
endmenu
@@ -4,3 +4,6 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
obj-$(CONFIG_PCI_J721E) += pci-j721e.o
+obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
+obj-$(CONFIG_PCIE_ROCKCHIP_EP) += pcie-rockchip-ep.o
+obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie-rockchip-host.o
similarity index 100%
rename from drivers/pci/controller/pcie-rockchip-ep.c
rename to drivers/pci/controller/cadence/pcie-rockchip-ep.c
similarity index 99%
rename from drivers/pci/controller/pcie-rockchip-host.c
rename to drivers/pci/controller/cadence/pcie-rockchip-host.c
@@ -36,7 +36,7 @@
#include <linux/reset.h>
#include <linux/regmap.h>
-#include "../pci.h"
+#include "../../pci.h"
#include "pcie-rockchip.h"
static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
similarity index 99%
rename from drivers/pci/controller/pcie-rockchip.c
rename to drivers/pci/controller/cadence/pcie-rockchip.c
@@ -19,7 +19,7 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
-#include "../pci.h"
+#include "../../pci.h"
#include "pcie-rockchip.h"
int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
similarity index 100%
rename from drivers/pci/controller/pcie-rockchip.h
rename to drivers/pci/controller/cadence/pcie-rockchip.h
The Rockchip PCIe host controller is in fact a Cadence based PCIe host. This is most evident by comparing the address translation registers. As a first step to merge the Rockchip driver into the Cadence driver, let's just move the Rockchip driver into the Cadence directoy. This at least makes the relationship obvious. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Tom Joseph <tjoseph@cadence.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Shawn Lin <shawn.lin@rock-chips.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rockchip@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> --- This is going to conflict at least with 'PCI: rockchip: Fix bus checks in rockchip_pcie_valid_device()' and the common ECAM defines. drivers/pci/controller/Kconfig | 28 ------------------- drivers/pci/controller/Makefile | 3 -- drivers/pci/controller/cadence/Kconfig | 28 +++++++++++++++++++ drivers/pci/controller/cadence/Makefile | 3 ++ .../{ => cadence}/pcie-rockchip-ep.c | 0 .../{ => cadence}/pcie-rockchip-host.c | 2 +- .../controller/{ => cadence}/pcie-rockchip.c | 2 +- .../controller/{ => cadence}/pcie-rockchip.h | 0 8 files changed, 33 insertions(+), 33 deletions(-) rename drivers/pci/controller/{ => cadence}/pcie-rockchip-ep.c (100%) rename drivers/pci/controller/{ => cadence}/pcie-rockchip-host.c (99%) rename drivers/pci/controller/{ => cadence}/pcie-rockchip.c (99%) rename drivers/pci/controller/{ => cadence}/pcie-rockchip.h (100%)