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([2a00:5f00:102:0:b16d:9752:8f38:7d6b]) by smtp.gmail.com with ESMTPSA id a17sm4008547wmj.9.2021.03.11.07.41.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 07:41:03 -0800 (PST) From: Emil Velikov To: Ezequiel Garcia , Philipp Zabel , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, Nicolas Ferre Cc: emil.l.velikov@gmail.com Subject: [PATCH v2 01/10] media: hantro: use G1_REG_INTERRUPT directly for the mpeg2 Date: Thu, 11 Mar 2021 15:40:46 +0000 Message-Id: <20210311154055.3496076-2-emil.l.velikov@gmail.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210311154055.3496076-1-emil.l.velikov@gmail.com> References: <20210311154055.3496076-1-emil.l.velikov@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210311_154104_523533_756C460E X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Emil Velikov Use the register directly over the existing SWREG(). Ideally we'll port the driver away from the local registers, but for now this is enough. For context - I was reading through the IRQ register handling across the variants. Signed-off-by: Emil Velikov --- drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c b/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c index 6386a3989bfe..0fd306806f16 100644 --- a/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_mpeg2_dec.c @@ -10,6 +10,7 @@ #include #include "hantro.h" #include "hantro_hw.h" +#include "hantro_g1_regs.h" #define G1_SWREG(nr) ((nr) * 4) @@ -20,7 +21,6 @@ #define G1_REG_REFER2_BASE G1_SWREG(16) #define G1_REG_REFER3_BASE G1_SWREG(17) #define G1_REG_QTABLE_BASE G1_SWREG(40) -#define G1_REG_DEC_E(v) ((v) ? BIT(0) : 0) #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) @@ -246,6 +246,5 @@ void hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx) hantro_end_prepare_run(ctx); - reg = G1_REG_DEC_E(1); - vdpu_write(vpu, reg, G1_SWREG(1)); + vdpu_write(vpu, G1_REG_INTERRUPT_DEC_E, G1_REG_INTERRUPT); }