| Message ID | 20210504084124.131884-2-benjamin.gaignard@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add driver for rk356x | expand |
On Tue, May 04, 2021 at 10:41:21AM +0200, Benjamin Gaignard wrote: > Convert Rockchip IOMMU to DT schema > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > version 2: > - Change maintainer > - Change reg maxItems > - Change interrupt maxItems > > .../bindings/iommu/rockchip,iommu.txt | 38 --------- > .../bindings/iommu/rockchip,iommu.yaml | 79 +++++++++++++++++++ > 2 files changed, 79 insertions(+), 38 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/iommu/rockchip,iommu.txt > create mode 100644 Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml > > diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt > deleted file mode 100644 > index 6ecefea1c6f9..000000000000 > --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt > +++ /dev/null > @@ -1,38 +0,0 @@ > -Rockchip IOMMU > -============== > - > -A Rockchip DRM iommu translates io virtual addresses to physical addresses for > -its master device. Each slave device is bound to a single master device, and > -shares its clocks, power domain and irq. > - > -Required properties: > -- compatible : Should be "rockchip,iommu" > -- reg : Address space for the configuration registers > -- interrupts : Interrupt specifier for the IOMMU instance > -- interrupt-names : Interrupt name for the IOMMU instance > -- #iommu-cells : Should be <0>. This indicates the iommu is a > - "single-master" device, and needs no additional information > - to associate with its master device. See: > - Documentation/devicetree/bindings/iommu/iommu.txt > -- clocks : A list of clocks required for the IOMMU to be accessible by > - the host CPU. > -- clock-names : Should contain the following: > - "iface" - Main peripheral bus clock (PCLK/HCL) (required) > - "aclk" - AXI bus clock (required) > - > -Optional properties: > -- rockchip,disable-mmu-reset : Don't use the mmu reset operation. > - Some mmu instances may produce unexpected results > - when the reset operation is used. > - > -Example: > - > - vopl_mmu: iommu@ff940300 { > - compatible = "rockchip,iommu"; > - reg = <0xff940300 0x100>; > - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "vopl_mmu"; > - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; > - clock-names = "aclk", "iface"; > - #iommu-cells = <0>; > - }; > diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml > new file mode 100644 > index 000000000000..0db208cf724a > --- /dev/null > +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml > @@ -0,0 +1,79 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Rockchip IOMMU > + > +maintainers: > + - Heiko Stuebner <heiko@sntech.de> > + > +description: |+ > + A Rockchip DRM iommu translates io virtual addresses to physical addresses for > + its master device. Each slave device is bound to a single master device and > + shares its clocks, power domain and irq. > + > + For information on assigning IOMMU controller to its peripheral devices, > + see generic IOMMU bindings. > + > +properties: > + compatible: > + const: rockchip,iommu > + > + reg: > + minItems: 1 > + maxItems: 2 What's the 2nd entry? If there's only 1 entry, then you don't have to describe what it is. If more than 1, then each entry has to be defined. > + > + interrupts: > + minItems: 1 > + maxItems: 2 Same here, though if interrupt-names defines them, that's good enough. > + > + interrupt-names: > + minItems: 1 > + maxItems: 2 Here we need the values. > + > + clocks: > + items: > + - description: Core clock > + - description: Interface clock > + > + clock-names: > + items: > + - const: aclk > + - const: iface > + > + "#iommu-cells": > + const: 0 > + > + rockchip,disable-mmu-reset: > + $ref: /schemas/types.yaml#/definitions/flag > + description: | > + Do not use the mmu reset operation. > + Some mmu instances may produce unexpected results > + when the reset operation is used. > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - "#iommu-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/rk3399-cru.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + vopl_mmu: iommu@ff940300 { > + compatible = "rockchip,iommu"; > + reg = <0xff940300 0x100>; > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "vopl_mmu"; > + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; > + clock-names = "aclk", "iface"; > + #iommu-cells = <0>; > + }; > -- > 2.25.1 >
diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt b/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt deleted file mode 100644 index 6ecefea1c6f9..000000000000 --- a/Documentation/devicetree/bindings/iommu/rockchip,iommu.txt +++ /dev/null @@ -1,38 +0,0 @@ -Rockchip IOMMU -============== - -A Rockchip DRM iommu translates io virtual addresses to physical addresses for -its master device. Each slave device is bound to a single master device, and -shares its clocks, power domain and irq. - -Required properties: -- compatible : Should be "rockchip,iommu" -- reg : Address space for the configuration registers -- interrupts : Interrupt specifier for the IOMMU instance -- interrupt-names : Interrupt name for the IOMMU instance -- #iommu-cells : Should be <0>. This indicates the iommu is a - "single-master" device, and needs no additional information - to associate with its master device. See: - Documentation/devicetree/bindings/iommu/iommu.txt -- clocks : A list of clocks required for the IOMMU to be accessible by - the host CPU. -- clock-names : Should contain the following: - "iface" - Main peripheral bus clock (PCLK/HCL) (required) - "aclk" - AXI bus clock (required) - -Optional properties: -- rockchip,disable-mmu-reset : Don't use the mmu reset operation. - Some mmu instances may produce unexpected results - when the reset operation is used. - -Example: - - vopl_mmu: iommu@ff940300 { - compatible = "rockchip,iommu"; - reg = <0xff940300 0x100>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vopl_mmu"; - clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml new file mode 100644 index 000000000000..0db208cf724a --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip IOMMU + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +description: |+ + A Rockchip DRM iommu translates io virtual addresses to physical addresses for + its master device. Each slave device is bound to a single master device and + shares its clocks, power domain and irq. + + For information on assigning IOMMU controller to its peripheral devices, + see generic IOMMU bindings. + +properties: + compatible: + const: rockchip,iommu + + reg: + minItems: 1 + maxItems: 2 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: Core clock + - description: Interface clock + + clock-names: + items: + - const: aclk + - const: iface + + "#iommu-cells": + const: 0 + + rockchip,disable-mmu-reset: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Do not use the mmu reset operation. + Some mmu instances may produce unexpected results + when the reset operation is used. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rk3399-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + vopl_mmu: iommu@ff940300 { + compatible = "rockchip,iommu"; + reg = <0xff940300 0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + };
Convert Rockchip IOMMU to DT schema Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> --- version 2: - Change maintainer - Change reg maxItems - Change interrupt maxItems .../bindings/iommu/rockchip,iommu.txt | 38 --------- .../bindings/iommu/rockchip,iommu.yaml | 79 +++++++++++++++++++ 2 files changed, 79 insertions(+), 38 deletions(-) delete mode 100644 Documentation/devicetree/bindings/iommu/rockchip,iommu.txt create mode 100644 Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml