diff mbox series

[1/2] arm64: dts: rockchip: add isp node for px30

Message ID 20210830141318.66744-1-heiko@sntech.de (mailing list archive)
State New, archived
Headers show
Series [1/2] arm64: dts: rockchip: add isp node for px30 | expand

Commit Message

Heiko Stübner Aug. 30, 2021, 2:13 p.m. UTC 
From: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>

Add the rkisp1 node and iommu for the px30 soc.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
---
 arch/arm64/boot/dts/rockchip/px30.dtsi | 41 ++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

Comments

Heiko Stübner Sept. 20, 2021, 2:28 p.m. UTC | #1 
On Mon, 30 Aug 2021 16:13:17 +0200, Heiko Stuebner wrote:
> Add the rkisp1 node and iommu for the px30 soc.

Applied, thanks!

[1/2] arm64: dts: rockchip: add isp node for px30
      commit: 8df7b4537dfb4c0a2a42de603927f5818cee0274
[2/2] arm64: dts: rockchip: hook up camera on px30-evb
      commit: 474a77395be201c80925efb7a0425fb28b0ba60b

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 64f643145688..500ef3af2a49 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -1189,6 +1189,47 @@  vopl_mmu: iommu@ff470f00 {
 		status = "disabled";
 	};
 
+	isp: isp@ff4a0000 {
+		compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
+		reg = <0x0 0xff4a0000 0x0 0x8000>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp", "mi", "mipi";
+		clocks = <&cru SCLK_ISP>,
+			 <&cru ACLK_ISP>,
+			 <&cru HCLK_ISP>,
+			 <&cru PCLK_ISP>;
+		clock-names = "isp", "aclk", "hclk", "pclk";
+		iommus = <&isp_mmu>;
+		phys = <&csi_dphy>;
+		phy-names = "dphy";
+		power-domains = <&power PX30_PD_VI>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
+	isp_mmu: iommu@ff4a8000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xff4a8000 0x0 0x100>;
+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power PX30_PD_VI>;
+		rockchip,disable-mmu-reset;
+		#iommu-cells = <0>;
+	};
+
 	qos_gmac: qos@ff518000 {
 		compatible = "rockchip,px30-qos", "syscon";
 		reg = <0x0 0xff518000 0x0 0x20>;