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[37.145.211.218]) by smtp.gmail.com with ESMTPSA id q189sm1859345ljb.68.2021.08.30.11.08.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Aug 2021 11:08:23 -0700 (PDT) From: Mikhail Rudenko To: linux-phy@lists.infradead.org Cc: linux-media@vger.kernel.org, Mikhail Rudenko , Rob Herring , Heiko Stuebner , Johan Jonker , Marc Zyngier , Helen Koike , Elaine Zhang , Shunqian Zheng , Robin Murphy , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] arm64: dts: rockchip: add mipi-dphy-tx1rx1 for rk3399 Date: Mon, 30 Aug 2021 21:07:54 +0300 Message-Id: <20210830180758.251390-6-mike.rudenko@gmail.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210830180758.251390-1-mike.rudenko@gmail.com> References: <20210830180758.251390-1-mike.rudenko@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210830_110825_281181_4E14B124 X-CRM114-Status: GOOD ( 10.35 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add DT node for RX mode of RK3399 TX1RX1 D-PHY. Signed-off-by: Mikhail Rudenko --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 3871c7fd83b0..2e4513275a87 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1902,6 +1902,21 @@ mipi1_in_vopl: endpoint@1 { }; }; + mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@ff968000 { + compatible = "rockchip,rk3399-mipi-dphy-tx1rx1"; + reg = <0x0 0xff968000 0x0 0x8000>; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru PCLK_VIO_GRF>, + <&cru PCLK_MIPI_DSI1>; + clock-names = "dphy-ref", "dphy-cfg", + "grf", "dsi"; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>;