From patchwork Wed Jan 26 14:55:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 12725198 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B71BCC2BA4C for ; Wed, 26 Jan 2022 15:11:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9i5GcL4VRFwsRLb2fPHIiS0lS4y317axhsUfysIc988=; b=5FiFBDnn9ROGPh +ciMuDDqwEePzrs0xkFrEsKDTWKq8nA4dmW3y815rXR44kCFXppEi8U/OKcCTrw7dWcDQN3m0qPOH nD1MrdLK0twT2d05wml03slZl8oohMll1P9FpWsLxSpjhnpyo2QaeT3L8ZIlQ+O1B/aN8SMPlz+G7 WjedawojDk5+T1y7YGX7WWkybaYNLkICwE9LnZYidI4lH9t6T7SyFjQE5EvqPlEsO0SLHMQLIVs7C sWTWCEEdMM5Fz5jO3A9DlEpogjtJ5Te0wbzqn57AXlZuWULBoos42mDXJfONEGoA4fM+nOfJiROBa v0+nm0A4o+4E5MZYb7wQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCjwu-00CA3M-OU; Wed, 26 Jan 2022 15:11:05 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCjku-00C4PS-Bi for linux-rockchip@bombadil.infradead.org; Wed, 26 Jan 2022 14:58:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=lGItTcetu29OtcNtfOgrlryiBkhrObz8X7RQ+AwZTpM=; b=Hde3EvKbuEFd7cE+Gsl4jWXcpw eZ65IFfa2wIHCLlm7vOtr3Y5p/ZMJkj299NqKhkS6UMIBWTf6kY8RUrb6pNIUtzUV0cmudCF8OTkz pgqAcuSN53P7mmMs86PB7N4esyw6jemzR8UVs5Zm/U7uVYdrpbn/77lbX16ZJk1QrfvOObfXOVdyA ipLQ4Ywr5DqNLFaSMNNX0LTdvYlhvVeMiMr5jWTF03l5rTZPcSVA6pgYnqgsNDdwGlTFpYsIe3Phf lmUuHUj0uOAuHquDni2WEAyGw1Pm0CnhS7QE1Xvkl1DIhFRxKHlghHFS9ERtA4Yj5Bzm12zwys0nV IxNMNGMQ==; Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nCjkj-003pia-PU for linux-rockchip@lists.infradead.org; Wed, 26 Jan 2022 14:58:39 +0000 Received: from dude02.hi.pengutronix.de ([2001:67c:670:100:1d::28]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nCjkc-0005fZ-An; Wed, 26 Jan 2022 15:58:22 +0100 Received: from sha by dude02.hi.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nCjka-002l7I-SX; Wed, 26 Jan 2022 15:58:20 +0100 From: Sascha Hauer To: dri-devel@lists.freedesktop.org Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@pengutronix.de, Andy Yan , Benjamin Gaignard , Michael Riesch , Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Peter Geis , Sascha Hauer Subject: [PATCH 25/27] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Date: Wed, 26 Jan 2022 15:55:47 +0100 Message-Id: <20220126145549.617165-26-s.hauer@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220126145549.617165-1-s.hauer@pengutronix.de> References: <20220126145549.617165-1-s.hauer@pengutronix.de> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::28 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-rockchip@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220126_145830_061314_79D1C3C8 X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On the rk3568 we have this (simplified) situation: .--------. .-----. .---------. -| hpll |--.--| /n |----|dclk_vop0|- `--------´ | `-----´ `---------´ | .-----. .---------. `--| /m |----|dclk_vop1|- | `-----´ `---------´ | .---------. `-------------|hdmi_ref |- `---------´ For the HDMI to work the HDMI reference clock needs to be the same as the pixel clock which means the dividers have be set to one. The last patch removed the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not changed on pixel clock changes. In order to allow the HDMI controller to set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the HDMI reference clock. With this the flow becomes: 1) HDMI controller driver sets the rate to its pixel clock which means hpll is set to the pixel clock 2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change the hpll clock anymore this means only the divider is adjusted to the desired value of dividing by one. Signed-off-by: Sascha Hauer --- drivers/clk/rockchip/clk-rk3568.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 7687c62d1fa8..63dfbeeeb06d 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1568,7 +1568,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = { RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS), GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0, RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS), - MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0, + MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT, RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS), };