| Message ID | 20220831182629.79255-3-sebastian.reichel@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RK3588 Power Domain Support | expand |
On Wed, Aug 31, 2022 at 08:26:25PM +0200, Sebastian Reichel wrote: > From: Finley Xiao <finley.xiao@rock-chips.com> > > Add all the power domains listed in the RK3588 TRM. > > Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > As mentioned in the cover letter I did not update this into dual > license, since there was no feedback from Rockchip :( Well then, I guess we'll stop taking Rockchip patches. Sorry, but what other leverage do I have? Rob
Hi, The devicetree binidng-headers should be dual-licensed, please change the license to GPL-2.0+ OR MIT. 在 2022/9/1 02:26, Sebastian Reichel 写道: > From: Finley Xiao <finley.xiao@rock-chips.com> > > Add all the power domains listed in the RK3588 TRM. > > Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > As mentioned in the cover letter I did not update this into dual > license, since there was no feedback from Rockchip :( > --- > include/dt-bindings/power/rk3588-power.h | 69 ++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > create mode 100644 include/dt-bindings/power/rk3588-power.h > > diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h > new file mode 100644 > index 000000000000..69f7e9060250 > --- /dev/null > +++ b/include/dt-bindings/power/rk3588-power.h > @@ -0,0 +1,69 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ > +#define __DT_BINDINGS_POWER_RK3588_POWER_H__ > + > +/* VD_LITDSU */ > +#define RK3588_PD_CPU_0 0 > +#define RK3588_PD_CPU_1 1 > +#define RK3588_PD_CPU_2 2 > +#define RK3588_PD_CPU_3 3 > + > +/* VD_BIGCORE0 */ > +#define RK3588_PD_CPU_4 4 > +#define RK3588_PD_CPU_5 5 > + > +/* VD_BIGCORE1 */ > +#define RK3588_PD_CPU_6 6 > +#define RK3588_PD_CPU_7 7 > + > +/* VD_NPU */ > +#define RK3588_PD_NPU 8 > +#define RK3588_PD_NPUTOP 9 > +#define RK3588_PD_NPU1 10 > +#define RK3588_PD_NPU2 11 > + > +/* VD_GPU */ > +#define RK3588_PD_GPU 12 > + > +/* VD_VCODEC */ > +#define RK3588_PD_VCODEC 13 > +#define RK3588_PD_RKVDEC0 14 > +#define RK3588_PD_RKVDEC1 15 > +#define RK3588_PD_VENC0 16 > +#define RK3588_PD_VENC1 17 > + > +/* VD_DD01 */ > +#define RK3588_PD_DDR01 18 > + > +/* VD_DD23 */ > +#define RK3588_PD_DDR23 19 > + > +/* VD_LOGIC */ > +#define RK3588_PD_CENTER 20 > +#define RK3588_PD_VDPU 21 > +#define RK3588_PD_RGA30 22 > +#define RK3588_PD_AV1 23 > +#define RK3588_PD_VOP 24 > +#define RK3588_PD_VO0 25 > +#define RK3588_PD_VO1 26 > +#define RK3588_PD_VI 27 > +#define RK3588_PD_ISP1 28 > +#define RK3588_PD_FEC 29 > +#define RK3588_PD_RGA31 30 > +#define RK3588_PD_USB 31 > +#define RK3588_PD_PHP 32 > +#define RK3588_PD_GMAC 33 > +#define RK3588_PD_PCIE 34 > +#define RK3588_PD_NVM 35 > +#define RK3588_PD_NVM0 36 > +#define RK3588_PD_SDIO 37 > +#define RK3588_PD_AUDIO 38 > +#define RK3588_PD_SECURE 39 > +#define RK3588_PD_SDMMC 40 > +#define RK3588_PD_CRYPTO 41 > +#define RK3588_PD_BUS 42 > + > +/* VD_PMU */ > +#define RK3588_PD_PMU1 43 > + > +#endif
diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h new file mode 100644 index 000000000000..69f7e9060250 --- /dev/null +++ b/include/dt-bindings/power/rk3588-power.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ +#define __DT_BINDINGS_POWER_RK3588_POWER_H__ + +/* VD_LITDSU */ +#define RK3588_PD_CPU_0 0 +#define RK3588_PD_CPU_1 1 +#define RK3588_PD_CPU_2 2 +#define RK3588_PD_CPU_3 3 + +/* VD_BIGCORE0 */ +#define RK3588_PD_CPU_4 4 +#define RK3588_PD_CPU_5 5 + +/* VD_BIGCORE1 */ +#define RK3588_PD_CPU_6 6 +#define RK3588_PD_CPU_7 7 + +/* VD_NPU */ +#define RK3588_PD_NPU 8 +#define RK3588_PD_NPUTOP 9 +#define RK3588_PD_NPU1 10 +#define RK3588_PD_NPU2 11 + +/* VD_GPU */ +#define RK3588_PD_GPU 12 + +/* VD_VCODEC */ +#define RK3588_PD_VCODEC 13 +#define RK3588_PD_RKVDEC0 14 +#define RK3588_PD_RKVDEC1 15 +#define RK3588_PD_VENC0 16 +#define RK3588_PD_VENC1 17 + +/* VD_DD01 */ +#define RK3588_PD_DDR01 18 + +/* VD_DD23 */ +#define RK3588_PD_DDR23 19 + +/* VD_LOGIC */ +#define RK3588_PD_CENTER 20 +#define RK3588_PD_VDPU 21 +#define RK3588_PD_RGA30 22 +#define RK3588_PD_AV1 23 +#define RK3588_PD_VOP 24 +#define RK3588_PD_VO0 25 +#define RK3588_PD_VO1 26 +#define RK3588_PD_VI 27 +#define RK3588_PD_ISP1 28 +#define RK3588_PD_FEC 29 +#define RK3588_PD_RGA31 30 +#define RK3588_PD_USB 31 +#define RK3588_PD_PHP 32 +#define RK3588_PD_GMAC 33 +#define RK3588_PD_PCIE 34 +#define RK3588_PD_NVM 35 +#define RK3588_PD_NVM0 36 +#define RK3588_PD_SDIO 37 +#define RK3588_PD_AUDIO 38 +#define RK3588_PD_SECURE 39 +#define RK3588_PD_SDMMC 40 +#define RK3588_PD_CRYPTO 41 +#define RK3588_PD_BUS 42 + +/* VD_PMU */ +#define RK3588_PD_PMU1 43 + +#endif