From patchwork Fri Sep 9 17:55:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 12972034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CCECECAAD3 for ; Fri, 9 Sep 2022 17:55:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IMrec87aE/8/EUfc6pH/O3iF9kSWqhKPwfEGZpGC3N0=; b=gFl+Vp1p3wKuq1 f2hqR0cQ14raC/vFeIPzOG8WoKqfxY26gYSK/PuSVfSBT0JYCf0I5cDZJzo8grCWOJBUafbRnog20 MVOmkwRWVkb9Xgmllko5fPUrppWmNEGBtQxY4vKQbkcllqP83J+/7nPFN6P7ny+Yt/lJsuhP5mIgj 3QA7IP+g+cgjtQrDSpt29ET7wcRAVueqB5GPYSxuv0gtxDFTYdh+80KO0jzTjTzHcX+EZ561/zFhg pKh5t2xv1ZR13KR/sjXUEU+6pPtI0lHKAGdp38NECNzwkwTAxLSrUS8ICYL/Vww8nowymhz1RoiWs k/Z9JPpyS+Vj2Uqb+P9w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWiEC-000u2I-P9; Fri, 09 Sep 2022 17:55:44 +0000 Received: from madras.collabora.co.uk ([46.235.227.172]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWiE5-000trW-Db for linux-rockchip@lists.infradead.org; Fri, 09 Sep 2022 17:55:41 +0000 Received: from jupiter.universe (dyndsl-095-033-168-128.ewe-ip-backbone.de [95.33.168.128]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 19C3C6601FDB; Fri, 9 Sep 2022 18:55:31 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1662746131; bh=XYYcbtJgv25KvQnOUHgNscwzxwqtYPVJyKex1PCPoKw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VzbRbkcivt7NIQpiBugNFNdEv6ZmfhdxCgwsUuEZJ2NnKxo2ayeAWSSfQRyZYjyq+ ZbqILIVwnLW+5rxZy7xe8CIvj0Nwppfwz2wwa7qJUYx2c40hlVOKTLsrNrcdEvBnr3 7oAQeRzHK3u2E8O0IKhOgrmIpBEKh2/Oja3rfS6G6e7p9eF4G+Jurc7QT8LeNB7abd qFrxN8HD6+UBsOoSwM95ZKzNTQNaXjEq8OCxRuC7/ybzldKNWWoY7jw/AaBhYidmei oLfedjfohQYkoA8Z5wtW1IHQhKXGz8omOrtvq6BS7qbWV/6IbSGa5c+Dx/FFmrE/iN T7e8A7vfaMm9w== Received: by jupiter.universe (Postfix, from userid 1000) id 28493480591; Fri, 9 Sep 2022 19:55:27 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Lee Jones Cc: Michael Turquette , Stephen Boyd , Linus Walleij , Mark Brown , Liam Girdwood , Alexandre Belloni , Alessandro Zummo , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sebastian Reichel , kernel@collabora.com, shengfei Xu Subject: [PATCHv3 10/14] pinctrl: rk805: add rk806 pinctrl support Date: Fri, 9 Sep 2022 19:55:18 +0200 Message-Id: <20220909175522.179175-11-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220909175522.179175-1-sebastian.reichel@collabora.com> References: <20220909175522.179175-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220909_105537_764976_59869730 X-CRM114-Status: GOOD ( 21.91 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add support for rk806 dvs pinctrl to the existing rk805 driver. This has been implemented using shengfei Xu's rk806 specific driver from the vendor tree as reference. Co-Developed-by: shengfei Xu Signed-off-by: shengfei Xu Reviewed-by: Linus Walleij Signed-off-by: Sebastian Reichel --- drivers/pinctrl/pinctrl-rk805.c | 189 ++++++++++++++++++++++++++++---- 1 file changed, 168 insertions(+), 21 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index 7c1f7408fb9a..2639a9ee82cd 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Pinctrl driver for Rockchip RK805 PMIC + * Pinctrl driver for Rockchip RK805/RK806 PMIC * * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. * * Author: Joseph Chen + * Author: Xu Shengfei * * Based on the pinctrl-as3722 driver */ @@ -44,6 +46,7 @@ struct rk805_pin_group { /* * @reg: gpio setting register; + * @fun_reg: functions select register; * @fun_mask: functions select mask value, when set is gpio; * @dir_mask: input or output mask value, when set is output, otherwise input; * @val_mask: gpio set value, when set is level high, otherwise low; @@ -56,6 +59,7 @@ struct rk805_pin_group { */ struct rk805_pin_config { u8 reg; + u8 fun_reg; u8 fun_msk; u8 dir_msk; u8 val_msk; @@ -80,22 +84,50 @@ enum rk805_pinmux_option { RK805_PINMUX_GPIO, }; +enum rk806_pinmux_option { + RK806_PINMUX_FUN0 = 0, + RK806_PINMUX_FUN1, + RK806_PINMUX_FUN2, + RK806_PINMUX_FUN3, + RK806_PINMUX_FUN4, + RK806_PINMUX_FUN5, +}; + enum { RK805_GPIO0, RK805_GPIO1, }; +enum { + RK806_GPIO_DVS1, + RK806_GPIO_DVS2, + RK806_GPIO_DVS3 +}; + static const char *const rk805_gpio_groups[] = { "gpio0", "gpio1", }; +static const char *const rk806_gpio_groups[] = { + "gpio_pwrctrl1", + "gpio_pwrctrl2", + "gpio_pwrctrl3", +}; + /* RK805: 2 output only GPIOs */ static const struct pinctrl_pin_desc rk805_pins_desc[] = { PINCTRL_PIN(RK805_GPIO0, "gpio0"), PINCTRL_PIN(RK805_GPIO1, "gpio1"), }; +/* RK806 */ +static const struct pinctrl_pin_desc rk806_pins_desc[] = { + PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"), + PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"), + PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"), +}; + static const struct rk805_pin_function rk805_pin_functions[] = { { .name = "gpio", @@ -105,6 +137,45 @@ static const struct rk805_pin_function rk805_pin_functions[] = { }, }; +static const struct rk805_pin_function rk806_pin_functions[] = { + { + .name = "pin_fun0", + .groups = rk806_gpio_groups, + .ngroups = ARRAY_SIZE(rk806_gpio_groups), + .mux_option = RK806_PINMUX_FUN0, + }, + { + .name = "pin_fun1", + .groups = rk806_gpio_groups, + .ngroups = ARRAY_SIZE(rk806_gpio_groups), + .mux_option = RK806_PINMUX_FUN1, + }, + { + .name = "pin_fun2", + .groups = rk806_gpio_groups, + .ngroups = ARRAY_SIZE(rk806_gpio_groups), + .mux_option = RK806_PINMUX_FUN2, + }, + { + .name = "pin_fun3", + .groups = rk806_gpio_groups, + .ngroups = ARRAY_SIZE(rk806_gpio_groups), + .mux_option = RK806_PINMUX_FUN3, + }, + { + .name = "pin_fun4", + .groups = rk806_gpio_groups, + .ngroups = ARRAY_SIZE(rk806_gpio_groups), + .mux_option = RK806_PINMUX_FUN4, + }, + { + .name = "pin_fun5", + .groups = rk806_gpio_groups, + .ngroups = ARRAY_SIZE(rk806_gpio_groups), + .mux_option = RK806_PINMUX_FUN5, + }, +}; + static const struct rk805_pin_group rk805_pin_groups[] = { { .name = "gpio0", @@ -118,6 +189,24 @@ static const struct rk805_pin_group rk805_pin_groups[] = { }, }; +static const struct rk805_pin_group rk806_pin_groups[] = { + { + .name = "gpio_pwrctrl1", + .pins = { RK806_GPIO_DVS1 }, + .npins = 1, + }, + { + .name = "gpio_pwrctrl2", + .pins = { RK806_GPIO_DVS2 }, + .npins = 1, + }, + { + .name = "gpio_pwrctrl3", + .pins = { RK806_GPIO_DVS3 }, + .npins = 1, + } +}; + #define RK805_GPIO0_VAL_MSK BIT(0) #define RK805_GPIO1_VAL_MSK BIT(1) @@ -132,6 +221,40 @@ static const struct rk805_pin_config rk805_gpio_cfgs[] = { }, }; +#define RK806_PWRCTRL1_DR BIT(0) +#define RK806_PWRCTRL2_DR BIT(1) +#define RK806_PWRCTRL3_DR BIT(2) +#define RK806_PWRCTRL1_DATA BIT(4) +#define RK806_PWRCTRL2_DATA BIT(5) +#define RK806_PWRCTRL3_DATA BIT(6) +#define RK806_PWRCTRL1_FUN GENMASK(2, 0) +#define RK806_PWRCTRL2_FUN GENMASK(6, 4) +#define RK806_PWRCTRL3_FUN GENMASK(2, 0) + +static struct rk805_pin_config rk806_gpio_cfgs[] = { + { + .fun_reg = RK806_SLEEP_CONFIG0, + .fun_msk = RK806_PWRCTRL1_FUN, + .reg = RK806_SLEEP_GPIO, + .val_msk = RK806_PWRCTRL1_DATA, + .dir_msk = RK806_PWRCTRL1_DR, + }, + { + .fun_reg = RK806_SLEEP_CONFIG0, + .fun_msk = RK806_PWRCTRL2_FUN, + .reg = RK806_SLEEP_GPIO, + .val_msk = RK806_PWRCTRL2_DATA, + .dir_msk = RK806_PWRCTRL2_DR, + }, + { + .fun_reg = RK806_SLEEP_CONFIG1, + .fun_msk = RK806_PWRCTRL3_FUN, + .reg = RK806_SLEEP_GPIO, + .val_msk = RK806_PWRCTRL3_DATA, + .dir_msk = RK806_PWRCTRL3_DR, + } +}; + /* generic gpio chip */ static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset) { @@ -289,19 +412,13 @@ static int _rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev, if (!pci->pin_cfg[offset].fun_msk) return 0; - if (mux == RK805_PINMUX_GPIO) { - ret = regmap_update_bits(pci->rk808->regmap, - pci->pin_cfg[offset].reg, - pci->pin_cfg[offset].fun_msk, - pci->pin_cfg[offset].fun_msk); - if (ret) { - dev_err(pci->dev, "set gpio%d GPIO failed\n", offset); - return ret; - } - } else { - dev_err(pci->dev, "Couldn't find function mux %d\n", mux); - return -EINVAL; - } + mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1; + ret = regmap_update_bits(pci->rk808->regmap, + pci->pin_cfg[offset].fun_reg, + pci->pin_cfg[offset].fun_msk, mux); + + if (ret) + dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux); return 0; } @@ -317,6 +434,22 @@ static int rk805_pinctrl_set_mux(struct pinctrl_dev *pctldev, return _rk805_pinctrl_set_mux(pctldev, offset, mux); } +static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); + + switch (pci->rk808->variant) { + case RK805_ID: + return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); + case RK806_ID: + return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5); + } + + return -ENOTSUPP; +} + static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, bool input) @@ -324,13 +457,6 @@ static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev); int ret; - /* switch to gpio function */ - ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO); - if (ret) { - dev_err(pci->dev, "set gpio%d mux failed\n", offset); - return ret; - } - /* set direction */ if (!pci->pin_cfg[offset].dir_msk) return 0; @@ -352,6 +478,7 @@ static const struct pinmux_ops rk805_pinmux_ops = { .get_function_name = rk805_pinctrl_get_func_name, .get_function_groups = rk805_pinctrl_get_func_groups, .set_mux = rk805_pinctrl_set_mux, + .gpio_request_enable = rk805_pinctrl_gpio_request_enable, .gpio_set_direction = rk805_pmx_gpio_set_direction, }; @@ -364,6 +491,7 @@ static int rk805_pinconf_get(struct pinctrl_dev *pctldev, switch (param) { case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_INPUT_ENABLE: arg = rk805_gpio_get(&pci->gpio_chip, pin); break; default: @@ -393,6 +521,12 @@ static int rk805_pinconf_set(struct pinctrl_dev *pctldev, rk805_gpio_set(&pci->gpio_chip, pin, arg); rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false); break; + case PIN_CONFIG_INPUT_ENABLE: + if (pci->rk808->variant != RK805_ID && arg) { + rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true); + break; + } + fallthrough; default: dev_err(pci->dev, "Properties not supported\n"); return -ENOTSUPP; @@ -448,6 +582,18 @@ static int rk805_pinctrl_probe(struct platform_device *pdev) pci->pin_cfg = rk805_gpio_cfgs; pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs); break; + case RK806_ID: + pci->pins = rk806_pins_desc; + pci->num_pins = ARRAY_SIZE(rk806_pins_desc); + pci->functions = rk806_pin_functions; + pci->num_functions = ARRAY_SIZE(rk806_pin_functions); + pci->groups = rk806_pin_groups; + pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups); + pci->pinctrl_desc.pins = rk806_pins_desc; + pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc); + pci->pin_cfg = rk806_gpio_cfgs; + pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs); + break; default: dev_err(&pdev->dev, "unsupported RK805 ID %lu\n", pci->rk808->variant); @@ -488,5 +634,6 @@ static struct platform_driver rk805_pinctrl_driver = { module_platform_driver(rk805_pinctrl_driver); MODULE_DESCRIPTION("RK805 pin control and GPIO driver"); +MODULE_AUTHOR("Xu Shengfei "); MODULE_AUTHOR("Joseph Chen "); MODULE_LICENSE("GPL v2");