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([103.51.72.15]) by smtp.gmail.com with ESMTPSA id l10-20020a170903120a00b0016f196209c9sm10479191plh.123.2022.09.25.23.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 23:14:32 -0700 (PDT) From: Anand Moon To: Rob Herring , Krzysztof Kozlowski , Heiko Stuebner Cc: Anand Moon , Chukun Pan , Michael Riesch , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH-next v1] arm64: dts: rockchip: Enable NVM Express PCIe controller on rock3a Date: Mon, 26 Sep 2022 06:14:18 +0000 Message-Id: <20220926061420.1248-1-linux.amoon@gmail.com> X-Mailer: git-send-email 2.37.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220925_231436_123942_19180F9E X-CRM114-Status: GOOD ( 11.82 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the nodes to enable the NVM Express PCIe controller on the Radxa ROCK3 Model A board. Cc: Chukun Pan Cc: Michael Riesch Signed-off-by: Anand Moon --- alarm@rock-3a:~$ lspci 0000:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3568 Remote Signal Processor (rev 01) 0002:00:00.0 PCI bridge: Rockchip Electronics Co., Ltd RK3568 Remote Signal Processor (rev 01) 0002:01:00.0 Non-Volatile memory controller: Micron/Crucial Technology P2 NVMe PCIe SSD (rev 01) --- .../boot/dts/rockchip/rk3568-rock-3a.dts | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index fb87a168fe96..44d85ee1631e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -79,6 +79,26 @@ vcc3v3_pcie: vcc3v3-pcie-regulator { vin-supply = <&vcc5v0_sys>; }; + /* pi6c pcie clock generator feeds both ports */ + vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c_03"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + vin-supply = <&vcc5v0_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0>, <3300000 0x1>; + }; + vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; @@ -546,6 +566,22 @@ &pcie2x1 { status = "okay"; }; +&pcie30phy { + data-lanes = <0 1 2 3>; + phy-supply = <&vcc3v3_pi6c_03>; + status = "okay"; +}; + +&pcie3x2 { + /* mPCIe slot */ + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x2m1_pins>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "okay"; +}; + &pinctrl { cam { vcc_cam_en: vcc_cam_en {