From patchwork Fri Sep 30 15:38:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 12995671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 91770C433FE for ; Fri, 30 Sep 2022 15:41:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fjlfHDxOfjdJwOcGbM1REvT1YVvI1GA1CQZcdc7EvRM=; b=vxm2WSfEp0ljSF nGpI2ymJmGWTETXQNrFKFeJs/Li1+V0xZBRC+OyNjXyZbngoghFX9IeM5XtbHk1Rwcd77eBlwvBME bFmkGontDUYbGggar19MopwSJL6g6T1UrKluGzlgUjHD+NGghz6YC1LLd5JlwzoAnal2wuYlOKawI dyMhmoJtIAjZ2TOtCUUZRDiKwDuu7vdBzv6Mitfi3ddKMf+1eU6ociKa8gS7sSS//6NXlNlqj5d0V OAXPP6muhfcrxXCmSKz3auSW2L5eNYuH4hCwClgGKxcIoh5oN0Xv+unYy87qPPmq0z12XnEbc3+UE iizwFtyTSHXFdmGjSOgw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeI8c-00AIhx-0m; Fri, 30 Sep 2022 15:41:18 +0000 Received: from madras.collabora.co.uk ([2a00:1098:0:82:1000:25:2eeb:e5ab]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oeI6V-00AHUq-8h; Fri, 30 Sep 2022 15:39:11 +0000 Received: from jupiter.universe (dyndsl-091-096-057-200.ewe-ip-backbone.de [91.96.57.200]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id 99DC766022EB; Fri, 30 Sep 2022 16:39:01 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1664552341; bh=gzxxKtgPz0zdv2mxZ6OWrJHbUBiLqyIjiAPbp8xPbpI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YKGjJG/ruRVmm0tnwFJbVi0129DlHgTp4Bg3bh+vxT+3eG9jhd4IsnAsG7wQU/uRH 9XwaJuXZo6DS767KGMqPk0nhssxTWAlOG98+qrwPr+Q1BAycO0Sst7DGxXU003H1AI kFjuk8T3g58HPsXdNukKiIPb2vNhJnsjshOJE8LmCk/IhXqnYMFtcRNN71dlag4VPS p/ufmJRO1uRbsMIfBg7KSEyhoUFUvd15960upI2S7j+3swl2jOdkaPDJMaLnN4TMt9 uAAs9kyhTrOUSrI+3hF/npltO+IRJJOpZg1wZSvJTUXwj+PfKyJe+pX6kB55cE5HCp DX4bNp93BeWAg== Received: by jupiter.universe (Postfix, from userid 1000) id 078F4480148; Fri, 30 Sep 2022 17:38:59 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Elaine Zhang , kernel@collabora.com, Sebastian Reichel Subject: [PATCHv2 3/9] dt-bindings: clock: add rk3588 cru bindings Date: Fri, 30 Sep 2022 17:38:51 +0200 Message-Id: <20220930153857.299396-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220930153857.299396-1-sebastian.reichel@collabora.com> References: <20220930153857.299396-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220930_083907_509734_3226BE4B X-CRM114-Status: GOOD ( 15.38 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Elaine Zhang Document the device tree bindings of the rockchip rk3588 SoC clock and reset unit. Signed-off-by: Elaine Zhang Signed-off-by: Sebastian Reichel Reviewed-by: Rob Herring --- .../bindings/clock/rockchip,rk3588-cru.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml new file mode 100644 index 000000000000..bb3856d75cdb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3588 Family Clock and Reset Control Module + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: | + The RK3588 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clock and reset IDs + are defined as preprocessor macros in dt-binding headers. + +properties: + compatible: + enum: + - rockchip,rk3588-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + phandle to the syscon managing the "general register files". It is used + for GRF muxes, if missing any muxes present in the GRF will not be + available. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0xfd7c0000 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + };