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Thu, 01 Dec 2022 12:37:02 -0800 (PST) Received: from localhost.localdomain ([76.244.6.13]) by smtp.gmail.com with ESMTPSA id r81-20020a4a3754000000b0049fd73ccf72sm2142142oor.42.2022.12.01.12.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Dec 2022 12:37:02 -0800 (PST) From: Chris Morgan To: linux-rockchip@lists.infradead.org Cc: devicetree@vger.kernel.org, maccraft123mc@gmail.com, heiko@sntech.de, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, Chris Morgan Subject: [PATCH 2/4] arm64: dts: rockchip: don't set cpll rate for Odroid Go Date: Thu, 1 Dec 2022 14:36:53 -0600 Message-Id: <20221201203655.1245-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221201203655.1245-1-macroalpha82@gmail.com> References: <20221201203655.1245-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221201_123706_551133_9C804459 X-CRM114-Status: GOOD ( 10.74 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Chris Morgan The Odroid Go Advance devicetree tries to set the rate for the cpll clock to 17MHz, which is not a supported rate. This fails, and triggers the error of "clk: couldn't set cpll clk rate to 17000000 (-22), current rate: 17000000" in the dmesg log. Remove the incorrect rate. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi index 60063f4bb366..802be64626d6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi @@ -192,14 +192,12 @@ &cru { assigned-clocks = <&cru PLL_NPLL>, <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, - <&cru PLL_CPLL>; + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; assigned-clock-rates = <1188000000>, <200000000>, <200000000>, <150000000>, <150000000>, - <100000000>, <200000000>, - <17000000>; + <100000000>, <200000000>; }; &display_subsystem {