diff mbox series

[PATCHv1,1/1] arm64: dts: rockchip: rk3588: add cache level information

Message ID 20230317174102.61209-1-sebastian.reichel@collabora.com (mailing list archive)
State New, archived
Headers show
Series [PATCHv1,1/1] arm64: dts: rockchip: rk3588: add cache level information | expand

Commit Message

Sebastian Reichel March 17, 2023, 5:41 p.m. UTC 
Add missing, mandatory cache-level information for RK3588.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Fixes init_of_cache_level() returning -EINVAL
---
 arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Heiko Stübner March 22, 2023, 11:40 p.m. UTC | #1 
On Fri, 17 Mar 2023 18:41:02 +0100, Sebastian Reichel wrote:
> Add missing, mandatory cache-level information for RK3588.
> 
> 

Applied, thanks!

[1/1] arm64: dts: rockchip: rk3588: add cache level information
      commit: b37115b6534c4027df75854a44b485596d368171

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 82dab5fcc3f0..0fb911704a64 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@ -440,6 +440,7 @@  l2_cache_l0: l2-cache-l0 {
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -448,6 +449,7 @@  l2_cache_l1: l2-cache-l1 {
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -456,6 +458,7 @@  l2_cache_l2: l2-cache-l2 {
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -464,6 +467,7 @@  l2_cache_l3: l2-cache-l3 {
 			cache-size = <131072>;
 			cache-line-size = <64>;
 			cache-sets = <512>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -472,6 +476,7 @@  l2_cache_b0: l2-cache-b0 {
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -480,6 +485,7 @@  l2_cache_b1: l2-cache-b1 {
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -488,6 +494,7 @@  l2_cache_b2: l2-cache-b2 {
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -496,6 +503,7 @@  l2_cache_b3: l2-cache-b3 {
 			cache-size = <524288>;
 			cache-line-size = <64>;
 			cache-sets = <1024>;
+			cache-level = <2>;
 			next-level-cache = <&l3_cache>;
 		};
 
@@ -504,6 +512,7 @@  l3_cache: l3-cache {
 			cache-size = <3145728>;
 			cache-line-size = <64>;
 			cache-sets = <4096>;
+			cache-level = <3>;
 		};
 	};