| Message ID | 20230525212712.255406-3-shreeya.patel@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RK3588 ADC support | expand |
Hi Shreeya,
kernel test robot noticed the following build errors:
[auto build test ERROR on rockchip/for-next]
[also build test ERROR on jic23-iio/togreg linus/master v6.4-rc3 next-20230525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Shreeya-Patel/iio-adc-rockchip_saradc-Add-callback-functions/20230526-053049
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
patch link: https://lore.kernel.org/r/20230525212712.255406-3-shreeya.patel%40collabora.com
patch subject: [PATCH v2 2/8] iio: adc: rockchip_saradc: Add support for RK3588
config: powerpc-allmodconfig
compiler: powerpc-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/5a4470a7d103b48a89f010f62135eed485969b03
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Shreeya-Patel/iio-adc-rockchip_saradc-Add-callback-functions/20230526-053049
git checkout 5a4470a7d103b48a89f010f62135eed485969b03
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 ~/bin/make.cross W=1 O=build_dir ARCH=powerpc SHELL=/bin/bash drivers/iio/adc/
If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305261340.VUt3YsQ2-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/iio/adc/rockchip_saradc.c: In function 'rockchip_saradc_start_v2':
>> drivers/iio/adc/rockchip_saradc.c:104:15: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
104 | val = FIELD_PREP(SARADC2_EN_END_INT, 1);
| ^~~~~~~~~~
cc1: some warnings being treated as errors
vim +/FIELD_PREP +104 drivers/iio/adc/rockchip_saradc.c
94
95 static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
96 {
97 int val;
98
99 if (info->reset)
100 rockchip_saradc_reset_controller(info->reset);
101
102 writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
103 writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
> 104 val = FIELD_PREP(SARADC2_EN_END_INT, 1);
105 val |= val << 16;
106 writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
107 val = FIELD_PREP(SARADC2_START, 1) |
108 FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
109 FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
110 val |= val << 16;
111 writel(val, info->regs + SARADC2_CONV_CON);
112 }
113
Il 25/05/23 23:27, Shreeya Patel ha scritto: > From: Simon Xue <xxm@rock-chips.com> > > Add new start and read functions to support rk3588 device. > Also, add a device compatible string for the same. > > Signed-off-by: Simon Xue <xxm@rock-chips.com> > Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> > --- > > Changes in v2 > - Add a from address. > - Create separate patches for adding new device support and changes to > the old device code. > - Make use of FIELD_PREP. > > drivers/iio/adc/rockchip_saradc.c | 69 +++++++++++++++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c > index 21f9d92a6af4..31637440be83 100644 > --- a/drivers/iio/adc/rockchip_saradc.c > +++ b/drivers/iio/adc/rockchip_saradc.c You're missing a header... #include <linux/bitfield.h> after adding that, you can get my Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Cheers, Angelo
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index 21f9d92a6af4..31637440be83 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -38,6 +38,22 @@ #define SARADC_TIMEOUT msecs_to_jiffies(100) #define SARADC_MAX_CHANNELS 8 +/* v2 registers */ +#define SARADC2_CONV_CON 0x0 +#define SARADC_T_PD_SOC 0x4 +#define SARADC_T_DAS_SOC 0xc +#define SARADC2_END_INT_EN 0x104 +#define SARADC2_ST_CON 0x108 +#define SARADC2_STATUS 0x10c +#define SARADC2_END_INT_ST 0x110 +#define SARADC2_DATA_BASE 0x120 + +#define SARADC2_EN_END_INT BIT(0) +#define SARADC2_START BIT(4) +#define SARADC2_SINGLE_MODE BIT(5) + +#define SARADC2_CONV_CHANNELS GENMASK(15, 0) + struct rockchip_saradc; struct rockchip_saradc_data { @@ -76,6 +92,25 @@ static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); } +static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) +{ + int val; + + if (info->reset) + rockchip_saradc_reset_controller(info->reset); + + writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); + writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); + val = FIELD_PREP(SARADC2_EN_END_INT, 1); + val |= val << 16; + writel_relaxed(val, info->regs + SARADC2_END_INT_EN); + val = FIELD_PREP(SARADC2_START, 1) | + FIELD_PREP(SARADC2_SINGLE_MODE, 1) | + FIELD_PREP(SARADC2_CONV_CHANNELS, chn); + val |= val << 16; + writel(val, info->regs + SARADC2_CONV_CON); +} + static void rockchip_saradc_start(struct rockchip_saradc *info, int chn) { info->data->start(info, chn); @@ -86,6 +121,18 @@ static int rockchip_saradc_read_v1(struct rockchip_saradc *info) return readl_relaxed(info->regs + SARADC_DATA); } +static int rockchip_saradc_read_v2(struct rockchip_saradc *info) +{ + int offset; + + /* Clear irq */ + writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST); + + offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4; + + return readl_relaxed(info->regs + offset); +} + static int rockchip_saradc_read(struct rockchip_saradc *info) { return info->data->read(info); @@ -248,6 +295,25 @@ static const struct rockchip_saradc_data rk3568_saradc_data = { .power_down = rockchip_saradc_power_down_v1, }; +static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = { + SARADC_CHANNEL(0, "adc0", 12), + SARADC_CHANNEL(1, "adc1", 12), + SARADC_CHANNEL(2, "adc2", 12), + SARADC_CHANNEL(3, "adc3", 12), + SARADC_CHANNEL(4, "adc4", 12), + SARADC_CHANNEL(5, "adc5", 12), + SARADC_CHANNEL(6, "adc6", 12), + SARADC_CHANNEL(7, "adc7", 12), +}; + +static const struct rockchip_saradc_data rk3588_saradc_data = { + .channels = rockchip_rk3588_saradc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels), + .clk_rate = 1000000, + .start = rockchip_saradc_start_v2, + .read = rockchip_saradc_read_v2, +}; + static const struct of_device_id rockchip_saradc_match[] = { { .compatible = "rockchip,saradc", @@ -261,6 +327,9 @@ static const struct of_device_id rockchip_saradc_match[] = { }, { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_data, + }, { + .compatible = "rockchip,rk3588-saradc", + .data = &rk3588_saradc_data, }, {}, };