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Wed, 18 Oct 2023 08:34:19 -0700 (PDT) Received: from localhost.localdomain ([75.28.21.198]) by smtp.gmail.com with ESMTPSA id h16-20020a4ad750000000b00581e090fd1fsm523782oot.8.2023.10.18.08.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 08:34:17 -0700 (PDT) From: Chris Morgan To: linux-rockchip@lists.infradead.org Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, sboyd@kernel.org, mturquette@baylibre.com, heiko@sntech.de, conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, Chris Morgan Subject: [PATCH 2/3] arm64: dts: rockchip: Update VPLL Frequency for RGB30 Date: Wed, 18 Oct 2023 10:33:56 -0500 Message-Id: <20231018153357.343142-3-macroalpha82@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018153357.343142-1-macroalpha82@gmail.com> References: <20231018153357.343142-1-macroalpha82@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231018_083420_536877_2C057743 X-CRM114-Status: GOOD ( 11.69 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Chris Morgan Set the VPLL frequency for the RGB30 to 292.5MHz to support running the 720x720 display panel at 59.97hz. Without this change, the panel runs at 59.08hz. Signed-off-by: Chris Morgan --- arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts index c7828c99a1bb..3ebc21608213 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-powkiddy-rgb30.dts @@ -68,7 +68,7 @@ &cru { assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>; assigned-clock-rates = <32768>, <1200000000>, - <200000000>, <108000000>; + <200000000>, <292500000>; }; &gpio_keys_control {