From patchwork Wed Jan 10 10:46:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues FRUCHET X-Patchwork-Id: 13515951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F2A2C3DA6E for ; Wed, 10 Jan 2024 10:48:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xGengCOHbittJ0VCnLfN/bpMbY/++VozaAfrUnnSb6k=; b=TEE+mi3K7DiQXn FZo2RWBnh+Jy68v4Zf5C7gUIpq0wOA3i4rUsjCNN/oubbtCwWPCEyMoEKgaX2NlrrEq8kuha/1K08 ev9wyPq49wAFIaJgb6IGGtQQoh3P8T5KLQMM778zm3G1v6lX4f8/ITYsZcHmMAAPZXWGICajJ3lIw Z53EC67MlXQ+pnn/qyHhKVMB5qIwLHT5hnel42d5DhqBqVRfOuNYUZksR2huu1PAoddfXMNOnY1N3 LE0TSPB0oDYpqxCjxWNU5F2Njn16iNebzYgSUpfDCutkA+QwKX44SB8nPL4Qch58V5Utvtln9A8iE +eZILz0qYkx9uhE9HMHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rNW8C-00B5pZ-0c; Wed, 10 Jan 2024 10:48:20 +0000 Received: from mx08-00178001.pphosted.com ([91.207.212.93] helo=mx07-00178001.pphosted.com) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rNW89-00B5nn-2G; Wed, 10 Jan 2024 10:48:19 +0000 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40A9VLDp006375; Wed, 10 Jan 2024 11:48:06 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=XYFUPkHCquAfdm1z7WpruAcO8XbDhwQU7gWaIj3jlwc=; b=si 5w8zvvujTnSCB03AnYmiGORVogLCdq91EPMdw6iymjR5O+ICM/jQyrYMFbz5hbFA 66zZ6FoIdsaeUsaDsbjYhbMm+wUQh3TpxgCUcWb//79aPs+XiQrU6JdUCpJvYAzA PzIAj/cDC9JRqLZQt7JwTc4vLLIEI3PftTQwYlPsd99f8kkDU2zlejYHNN23nQV8 jPgDBQOQqo/B1izhWB2UfZ6TRa7ek9A0eptbsMs0Wd8N+5gEGnJrZ/KfXrq3dobl eGENXqC6p7NfP5AB5AGolb1ItKRW1SqJrsYIEX04HW8o82EoVwFcdQ3l5heXX2K6 IOxk4qkB81SEyN2MEdiQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3vexmffv8v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:48:05 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1020710002A; Wed, 10 Jan 2024 11:48:05 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F132A26C050; Wed, 10 Jan 2024 11:48:04 +0100 (CET) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 10 Jan 2024 11:48:04 +0100 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Andrzej Pietrasiewicz , Nicolas Dufresne , Sakari Ailus , Benjamin Gaignard , Laurent Pinchart , Daniel Almeida , Benjamin Mugnier , Heiko Stuebner , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Marco Felsch , Adam Ford Subject: [RESEND PATCH v6 5/5] arm64: dts: st: add video encoder support to stm32mp255 Date: Wed, 10 Jan 2024 11:46:42 +0100 Message-ID: <20240110104642.532011-6-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240110104642.532011-1-hugues.fruchet@foss.st.com> References: <20240110104642.532011-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-05_08,2024-01-05_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240110_024818_023935_B42552CD X-CRM114-Status: UNSURE ( 9.98 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add VENC hardware video encoder support to STM32MP255. Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index cd6c4f627739..1584debca7f5 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -58,6 +58,12 @@ ck_icn_p_vdec: ck-icn-p-vdec { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index aea5096dac3c..17f197c5b22b 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -14,6 +14,13 @@ vdec: vdec@480d0000 { interrupts = ; clocks = <&ck_icn_p_vdec>; }; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupts = ; + clocks = <&ck_icn_ls_mcu>; + }; }; }; };