diff mbox series

[3/4] clk: rockchip: rk3568: Add PLL rate for 128MHz

Message ID 20240123212111.202146-4-macroalpha82@gmail.com (mailing list archive)
State New, archived
Headers show
Series Add Support for RK3566 Anbernic RG-ARC | expand

Commit Message

Chris Morgan Jan. 23, 2024, 9:21 p.m. UTC 
From: Chris Morgan <macromorgan@hotmail.com>

Add PLL rate for 128MHz to allow the panel for the Anbernic RG-ARC
series to run at 60hz.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 drivers/clk/rockchip/clk-rk3568.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index b786ddc9af2a..8cb21d10beca 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -78,6 +78,7 @@  static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
 	RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
 	RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
 	RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
+	RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),
 	RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
 	RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
 	RK3036_PLL_RATE(115200000, 1, 24, 5, 1, 1, 0),