| Message ID | 20240422133502.2592975-1-heiko@sntech.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] arm64: dts: rockchip: add PCIe3 support on rk3588-jaguar | expand |
Hi Heiko, On 2024-04-22 15:35, Heiko Stuebner wrote: > From: Heiko Stuebner <heiko.stuebner@cherry.de> > > The Jaguar SBC provides an M.2 slot connected to the pcie3 controller. > In contrast to a number of other boards the pcie-refclk is gpio-controlled, > so the necessary clock and is added to the list of pcie3 clocks. > > Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> > Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> > --- > changes in v3: > - drop unnecessary pinctrl comment (Quentin) > - add Quentin's review > > changes in v2: > - "an" M.2 slot (Dragan) > - pinctrl for refclk-en and reset pin (Quentin) > - don't repurpose the pcie30x4_pins pinctrl entry for only wake (Quentin) > > .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++ > 1 file changed, 59 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts > index 4076c92668ba..0ad53d7768a3 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts > @@ -72,6 +72,27 @@ led-1 { > }; > }; > > + /* > + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE > + * clock generator. > + * The clock output is gated via the OE pin on the clock generator. > + * This is modeled as a fixed-clock plus a gpio-gate-clock. > + */ > + pcie_refclk_gen: pcie-refclk-gen-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <1000000000>; This should probably be 100000000 (100 MHz) and not 1 GHz? Regards, Jonas > + }; > + > + pcie_refclk: pcie-refclk-clock { > + compatible = "gpio-gate-clock"; > + clocks = <&pcie_refclk_gen>; > + #clock-cells = <0>; > + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */ > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie30x4_clkreqn_m0>; > + }; > + > pps { > compatible = "pps-gpio"; > gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; > @@ -358,6 +379,30 @@ &pcie2x1l0 { > status = "okay"; > }; > > +&pcie30phy { > + status = "okay"; > +}; > + > +&pcie3x4 { > + /* > + * The board has a gpio-controlled "pcie_refclk" generator, > + * so add it to the list of clocks. > + */ > + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, > + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, > + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, > + <&pcie_refclk>; > + clock-names = "aclk_mst", "aclk_slv", > + "aclk_dbi", "pclk", > + "aux", "pipe", > + "ref"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>; > + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */ > + vpcie3v3-supply = <&vcc3v3_mdot2>; > + status = "okay"; > +}; > + > &pinctrl { > emmc { > emmc_reset: emmc-reset { > @@ -376,6 +421,20 @@ led1_pin: led1-pin { > rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; > }; > }; > + > + pcie30x4 { > + pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { > + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + pcie30x4_perstn_m0: pcie30x4-perstn-m0 { > + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > + pcie30x4_waken_m0: pcie30x4-waken-m0 { > + rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; > + }; > + }; > }; > > &saradc {
Hi Jonas, Heiko, On 4/22/24 20:36, Jonas Karlman wrote: > Hi Heiko, > > On 2024-04-22 15:35, Heiko Stuebner wrote: >> From: Heiko Stuebner <heiko.stuebner@cherry.de> >> >> The Jaguar SBC provides an M.2 slot connected to the pcie3 controller. >> In contrast to a number of other boards the pcie-refclk is gpio-controlled, >> so the necessary clock and is added to the list of pcie3 clocks. >> >> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> >> Reviewed-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> >> --- >> changes in v3: >> - drop unnecessary pinctrl comment (Quentin) >> - add Quentin's review >> >> changes in v2: >> - "an" M.2 slot (Dragan) >> - pinctrl for refclk-en and reset pin (Quentin) >> - don't repurpose the pcie30x4_pins pinctrl entry for only wake (Quentin) >> >> .../arm64/boot/dts/rockchip/rk3588-jaguar.dts | 59 +++++++++++++++++++ >> 1 file changed, 59 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts >> index 4076c92668ba..0ad53d7768a3 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts >> +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts >> @@ -72,6 +72,27 @@ led-1 { >> }; >> }; >> >> + /* >> + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE >> + * clock generator. >> + * The clock output is gated via the OE pin on the clock generator. >> + * This is modeled as a fixed-clock plus a gpio-gate-clock. >> + */ >> + pcie_refclk_gen: pcie-refclk-gen-clock { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-frequency = <1000000000>; > > This should probably be 100000000 (100 MHz) and not 1 GHz? > Good catch, we also need to fix this for Tiger where the same mistake was made it seems :/ Wondering if we couldn't have some kind of constant to make it more readable in DTSes? E.g. #define 1K 1000 #define 1Ki 1024 #define 1M 1000000 #define 1Mi 1048576 And in the DT we could simply have <(100 * 1M)> wherever appropriate? Thanks, Quentin
Hello Quentin, On 2024-04-23 11:10, Quentin Schulz wrote: > Wondering if we couldn't have some kind of constant to make it more > readable in DTSes? E.g. > > #define 1K 1000 > #define 1Ki 1024 > #define 1M 1000000 > #define 1Mi 1048576 > > And in the DT we could simply have <(100 * 1M)> wherever appropriate? Hmm... Perhaps "<(100M)>" would be even better? It would require more thorough changes, though.
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts index 4076c92668ba..0ad53d7768a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -72,6 +72,27 @@ led-1 { }; }; + /* + * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE + * clock generator. + * The clock output is gated via the OE pin on the clock generator. + * This is modeled as a fixed-clock plus a gpio-gate-clock. + */ + pcie_refclk_gen: pcie-refclk-gen-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + pcie_refclk: pcie-refclk-clock { + compatible = "gpio-gate-clock"; + clocks = <&pcie_refclk_gen>; + #clock-cells = <0>; + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; /* PCIE30X4_CLKREQN_M0 */ + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m0>; + }; + pps { compatible = "pps-gpio"; gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; @@ -358,6 +379,30 @@ &pcie2x1l0 { status = "okay"; }; +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + /* + * The board has a gpio-controlled "pcie_refclk" generator, + * so add it to the list of clocks. + */ + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, + <&pcie_refclk>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe", + "ref"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_waken_m0 &pcie30x4_perstn_m0>; + reset-gpios = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTN_M0 */ + vpcie3v3-supply = <&vcc3v3_mdot2>; + status = "okay"; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -376,6 +421,20 @@ led1_pin: led1-pin { rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + pcie30x4 { + pcie30x4_clkreqn_m0: pcie30x4-clkreqn-m0 { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_perstn_m0: pcie30x4-perstn-m0 { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie30x4_waken_m0: pcie30x4-waken-m0 { + rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; + }; + }; }; &saradc {