From patchwork Wed May 8 13:13:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13658717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9D87FC04FFE for ; Wed, 8 May 2024 13:14:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jamFWqZ37RVbZ8+tYkM/G8Xzl711L7R7dEzSppqzdrw=; b=jQ+/CH/XiXjIur Cd/M+SScJsRPwyK9pFTZtbyaezRkkMWeN+SB6DqkB3Fn4X4R5Mdbq/Y01G2nulDDW8qPciQgUkDMR XfouIs42cFHoVhiXr210SDIzh2tPA7hEyzPM9G8Q7mHDMU9N7ijUitjFpxPxeNsKvMIc3yQUaHgeH FaK2Ug468WwvD5wm9IpAGiHUuU29vk2/EEjlm+JSROtfDrS+gAYafzFQZtf31dpdximEdnd7SOl3H Gj9pnvHWFMgxknKnBdKhcu7EopjNhLtiZcq6Ce0zqvrBqKzkumYAYqovgdkD53CzCeP7Zb0/ey5P6 /Ee55EzxhCl8ZqGYK4nA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4h89-0000000Fano-1FPn; Wed, 08 May 2024 13:14:45 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s4h82-0000000FaiQ-05YU for linux-rockchip@lists.infradead.org; Wed, 08 May 2024 13:14:44 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 075CCCE18E3; Wed, 8 May 2024 13:14:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4D0A4C4AF17; Wed, 8 May 2024 13:14:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1715174075; bh=4qN66Ir2UFp9Lf/FY4N/yTmNKplsIfb7tfx/17jEJAs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=H3vDS/ZMSu2jc/jka1+zMAJzWeo1JXgkRQQskyMCMxX62PRtYTOIOhHu8i9X81GAm +Z5zN3lTn2Qph8nyMUcuQIeDOdnvsUhxp4eE3VGA6cgYAEN3uS4kSBWff686u+u+f+ Zerrus9eC4o6EwKFHsTKCMtwGupLE1wl+G2TezU4rwJ+w3hvnbGFtUgBZYVDHrwJuT Tm03m0GYeON5ewFn3k/Jco3d6+bUQ2GrHFwL+bXbd3VK8Ead/a8wX6imIl79hdi0U2 09z1rpAp4/ffp8Oou0axIxtDb2RjKy7KkvSXhec+GQpNbKdktGoRo1wMb4wco7/wY5 pAp3XxYloP1xQ== From: Niklas Cassel Date: Wed, 08 May 2024 15:13:44 +0200 Subject: [PATCH v3 13/13] arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode MIME-Version: 1.0 Message-Id: <20240508-rockchip-pcie-ep-v1-v3-13-1748e202b084@kernel.org> References: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> In-Reply-To: <20240508-rockchip-pcie-ep-v1-v3-0-1748e202b084@kernel.org> To: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Niklas Cassel , Kishon Vijay Abraham I , Arnd Bergmann , Damien Le Moal , Jon Lin , Shawn Lin , Simon Xue Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3453; i=cassel@kernel.org; h=from:subject:message-id; bh=4qN66Ir2UFp9Lf/FY4N/yTmNKplsIfb7tfx/17jEJAs=; b=kA0DAAoWyWQxo5nGTXIByyZiAGY7en+iU336wmdzkB6v5qlNz4tNEY6beo6f2OZq/+SyqI20f Ih1BAAWCgAdFiEETfhEv3OLR5THIdw8yWQxo5nGTXIFAmY7en8ACgkQyWQxo5nGTXK7XQD+PmFy Ydn/rF0xGmAkuXJHReuOBaNrXhf01lI4aa6pweUA/iVGALA3enh08RohJX+udFsce2YzMIbCO4t VB3hVI8kK X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240508_061438_581771_93E0716A X-CRM114-Status: GOOD ( 16.05 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add rock5b overlays for PCIe endpoint mode support. If using the rock5b as an endpoint against a normal PC, only the rk3588-rock-5b-pcie-ep.dtbo needs to be applied. If using two rock5b:s, with one board as EP and the other board as RC, rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to be applied to the respective boards. Signed-off-by: Niklas Cassel --- arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ 3 files changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f906a868b71a..d827432d5111 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb @@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_rk3588-rock-5b += -@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +};