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AJvYcCXm1UHuC6uxOOaSdXLfB88l/XYAHoBHX/lQi2WQUZqJjKzaJ1Nu7X0WJE1tdB/dnMacpwti3FYnX9KGCybxh0EAhkKyIptMQPqIkp56moxXimAin30XhLfyfeFC99lFbKcLLbyvT1tYnN8AmtTf45ApNm8UKeMScMs= X-Gm-Message-State: AOJu0YyjTayUgNRP/7IPDaLxAvb5zSXSX8DHmY5QbcXUKjVKNiJSnXrk 8Ez4KaT5lPdIORS+HyKkPPh/9phu+DNmjjS6GCEhaBOml27AuaI= X-Google-Smtp-Source: AGHT+IGvhcnG7M1Vbx/YQj99uXW0A5K4R73XVFCAylehvWPGYqkTm8EPKbShM4S7aRYehR6yW6Nflg== X-Received: by 2002:a05:6512:5d3:b0:52b:51f9:a37d with SMTP id 2adb3069b0e04-52bab5084b1mr1671148e87.56.1717608118030; Wed, 05 Jun 2024 10:21:58 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:34f:df25:1c86:f2e7]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31c6d594sm9666663a12.69.2024.06.05.10.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 10:21:57 -0700 (PDT) From: Alex Bee To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH 3/3] ARM: dts: rockchip: Add SFC for RK3128 Date: Wed, 5 Jun 2024 19:21:54 +0200 Message-ID: <20240605172154.193047-4-knaerzche@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240605172154.193047-1-knaerzche@gmail.com> References: <20240605172154.193047-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240605_102204_310061_C478A6DD X-CRM114-Status: GOOD ( 10.44 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the Serial Flash Controller and it's pincontrols. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index a7ab0904564f..22e2a35dedb1 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -399,6 +399,15 @@ usb_host_ohci: usb@101e0000 { status = "disabled"; }; + sfc: spi@1020c000 { + compatible = "rockchip,sfc"; + reg = <0x1020c000 0x8000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -1155,6 +1164,32 @@ sdmmc_bus4: sdmmc-bus4 { }; }; + sfc { + sfc_bus2: sfc-bus2 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>; + }; + + sfc_bus4: sfc-bus4 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>, + <1 RK_PD2 3 &pcfg_pull_default>, + <1 RK_PD3 3 &pcfg_pull_default>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = <2 RK_PA2 3 &pcfg_pull_default>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = <2 RK_PA3 3 &pcfg_pull_default>; + }; + }; + spdif { spdif_tx: spdif-tx { rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;