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AJvYcCVfDJtbcufMySI63/ybCFgEJapCUsFYjE4+7FLiL6vH71QDWqO4pLn4cdnclk6Z3TXKre46tMakALHR5pAEi3/abuy9MeGBLMTe3js0OMIEJedt7ar5gzyHtJ6vWrt2mgfa7c9uR1bQcYChJB69ccfOSZz6PmCZkQQ= X-Gm-Message-State: AOJu0Ywyd81gO8gG+yTA64WHW9ISrf3s6E5ZKhknUYzI/BmGWsAsvUs9 APvOAjvuUvjZN+jQRieyrGJ0VIWKG5gqpzkPYF16reisTK8mqYk= X-Google-Smtp-Source: AGHT+IFCUf/nSWcFwovwvBwGIMkEfxcyaPdZQUK7IjGCB4qaZIM7Vbj8k1JhhipZFwk6qW+PghjHTw== X-Received: by 2002:a5d:5886:0:b0:357:bd78:4954 with SMTP id ffacd0b85a97d-35e8833a4ebmr3356057f8f.30.1717620738877; Wed, 05 Jun 2024 13:52:18 -0700 (PDT) Received: from U4.lan ([2a02:810b:f40:4600:5211:58fe:dfef:c48c]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6c71bb5affsm72265866b.147.2024.06.05.13.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Jun 2024 13:52:18 -0700 (PDT) From: Alex Bee To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Michael Turquette , Stephen Boyd , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Alex Bee Subject: [PATCH v2 5/5] ARM: dts: rockchip: Add SFC for RK3128 Date: Wed, 5 Jun 2024 22:52:09 +0200 Message-ID: <20240605205209.232005-11-knaerzche@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240605205209.232005-1-knaerzche@gmail.com> References: <20240605205209.232005-1-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240605_135222_062730_DA586B75 X-CRM114-Status: GOOD ( 10.18 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add the Serial Flash Controller and it's pincontrols. Signed-off-by: Alex Bee --- changes since v1: - none arch/arm/boot/dts/rockchip/rk3128.dtsi | 35 ++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index a7ab0904564f..22e2a35dedb1 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -399,6 +399,15 @@ usb_host_ohci: usb@101e0000 { status = "disabled"; }; + sfc: spi@1020c000 { + compatible = "rockchip,sfc"; + reg = <0x1020c000 0x8000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -1155,6 +1164,32 @@ sdmmc_bus4: sdmmc-bus4 { }; }; + sfc { + sfc_bus2: sfc-bus2 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>; + }; + + sfc_bus4: sfc-bus4 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>, + <1 RK_PD2 3 &pcfg_pull_default>, + <1 RK_PD3 3 &pcfg_pull_default>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = <2 RK_PA2 3 &pcfg_pull_default>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = <2 RK_PA3 3 &pcfg_pull_default>; + }; + }; + spdif { spdif_tx: spdif-tx { rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;