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Each component of PCIe communication have the following control signals: PERST, WAKE, CLKREQ, and REFCLK. These signals work to generate high-speed signals and communicate with other PCIe devices. Used by root complex to endpoint depending on the power state. PERST is referred to as a fundamental reset. PERST should be held low until all the power rails in the system and the reference clock are stable. A transition from low to high in this signal usually indicates the beginning of link initialization. WAKE signal is an active-low signal that is used to return the PCIe interface to an active state when in a low-power state. CLKREQ signal is also an active-low signal and is used to request the reference clock. Rename node from 'pcie2' to 'pcie20x1' to align with schematic nomenclature. Signed-off-by: Anand Moon --- v4: rebase on master, used RK_FUNC_GPIO GPIO function instead of PIN number. V3: New patch. --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index eeae14842b71..813a28b8916e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -326,7 +326,7 @@ &pcie2x1l0 { &pcie2x1l2 { pinctrl-names = "default"; - pinctrl-0 = <&pcie2_2_rst>; + pinctrl-0 = <&pcie20x12_pins>; reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; @@ -363,9 +363,15 @@ hp_detect: hp-detect { }; }; - pcie2 { - pcie2_2_rst: pcie2-2-rst { - rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + pcie20x1 { + pcie20x12_pins: pcie20x12-pins { + rockchip,pins = + /* PCIE20_1_2_CLKREQn_M1_L */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, + /* PCIE_PERST_L */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + /* PCIE20_1_2_WAKEn_M1_L */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; }; };