@@ -86,29 +86,13 @@ vcc12v_dcin: vcc12v-dcin-regulator {
regulator-boot-on;
};
- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd0v9";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <900000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
- compatible = "regulator-fixed";
- regulator-name = "pcie30_avdd1v8";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc3v3_sys>;
- };
-
/* pi6c pcie clock generator */
vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren_h>;
regulator-name = "vcc3v3_pi6c_03";
regulator-always-on;
regulator-boot-on;
@@ -117,16 +101,13 @@ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
vin-supply = <&vcc5v0_sys>;
};
- vcc3v3_pcie: vcc3v3-pcie-regulator {
+ /* actually fed by vcc5v0_sys, dependent on pi6c clock generator */
+ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
compatible = "regulator-fixed";
- enable-active-high;
- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_enable_h>;
- regulator-name = "vcc3v3_pcie";
+ regulator-name = "vcc3v3_pcie30x1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- vin-supply = <&vcc5v0_sys>;
+ vin-supply = <&vcc3v3_pi6c_03>;
};
vcc3v3_sys: vcc3v3-sys-regulator {
@@ -617,7 +598,7 @@ &pcie3x2 {
pinctrl-names = "default";
pinctrl-0 = <&pcie30x2m1_pins>;
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
- vpcie3v3-supply = <&vcc3v3_pcie>;
+ vpcie3v3-supply = <&vcc3v3_pcie30x1>;
status = "okay";
};
@@ -653,7 +634,7 @@ led_user_en: led_user_en {
};
pcie {
- pcie_enable_h: pcie-enable-h {
+ pcie_pwren_h: pcie-pwren-h {
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -670,6 +651,18 @@ pcie20m1_pins: pcie20m1-pins {
};
};
+ pcie30x2 {
+ pcie30x2m1_pins: pcie30x2m1-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm1 */
+ <2 RK_PD4 4 &pcfg_pull_none>,
+ /* pcie30x2_perstnm1 */
+ <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>,
+ /* pcie30x2_wakenm1 */
+ <2 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int: pmic_int {
rockchip,pins =
on Radxa ROCK 3A, GPIO0_D4 is used to enable both pi6c PCIe clock generator and "vcc3v3_pcie" regulator (PCIe3 M.2 M key connector). since pi6c needs to be enabled before using PCIe3, GPIO0_D4 need to be controlled by "vcc3v3_pi6c_03" regulator. then, make "vcc3v3_pi6c_03" vin-supply for "vcc3v3_pcie30x1". also, "pcie30_avdd0v9" and "pcie30_avdd1v8" are unused. remove them. changes for pinctrl are to claim all 3 pins instead of only reset pin as like as rk3568-rock-3b.dts. Fixes: 0522cd811220 ("arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a") Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> --- Changes in v2: - split patches for PCIe2 and PCIe3 - change regulator name from "vcc3v3_pcie" to "vcc3v3_pcie30x1" - add comment for vin-supply of "vcc3v3_pcie30x1" regulator - remove unused "pcie30_avdd0v9" and "pcie30_avdd1v8" - fix pinctrl node name to overwrite rk3568-pinctrl.dtsi --- .../boot/dts/rockchip/rk3568-rock-3a.dts | 51 ++++++++----------- 1 file changed, 22 insertions(+), 29 deletions(-)