| Message ID | 20240918073236.648-1-naoki@radxa.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/2] arm64: dts: rockchip: change pinctrl-0 name in pcie3x1 for Radxa E25 | expand |
Hi, can anyone review this series? Best regards, -- FUKAUMI Naoki Radxa Computer (Shenzhen) Co., Ltd. On 9/18/24 16:32, FUKAUMI Naoki wrote: > to avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name. > > Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> > --- > Changes in v2: > - new > --- > arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts > index 84a0789fad96a..bf8f2d8e9e2a1 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts > @@ -123,7 +123,7 @@ &pcie30phy { > &pcie3x1 { > num-lanes = <1>; > pinctrl-names = "default"; > - pinctrl-0 = <&pcie30x1m0_pins>; > + pinctrl-0 = <&pcie30x1_reset_h>; > reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; > vpcie3v3-supply = <&vcc3v3_minipcie>; > status = "okay"; > @@ -148,6 +148,10 @@ pcie30x1_enable_h: pcie30x1-enable-h { > rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; > }; > > + pcie30x1_reset_h: pcie30x1-reset-h { > + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; > + }; > + > pcie30x2_reset_h: pcie30x2-reset-h { > rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; > };
On Wed, 18 Sep 2024 16:32:35 +0900, FUKAUMI Naoki wrote: > to avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name. > > Applied, thanks! [1/2] arm64: dts: rockchip: change pinctrl-0 name in pcie3x1 for Radxa E25 commit: be41da78a9738514d3b6c1acfaf156bbf380ce57 Didn't take patch2. As you know from the sdmmc runtime-pm thread you were in too, that whole thing is still in flux, so using cd-gpios does provide us with the safest and power efficient way for card-detect. Best regards,
Hi, On 11/11/24 05:13, Heiko Stuebner wrote: > On Wed, 18 Sep 2024 16:32:35 +0900, FUKAUMI Naoki wrote: >> to avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name. >> >> > > Applied, thanks! > > [1/2] arm64: dts: rockchip: change pinctrl-0 name in pcie3x1 for Radxa E25 > commit: be41da78a9738514d3b6c1acfaf156bbf380ce57 > > Didn't take patch2. As you know from the sdmmc runtime-pm thread you were > in too, that whole thing is still in flux, so using cd-gpios does provide > us with the safest and power efficient way for card-detect. I think that was only for RK3588 series. on RK356x boards, CD is working without cd-gpios, but it may have power efficient issue as like as RK3588, right? Best Regards, -- FUKAUMI Naoki Radxa Computer (Shenzhen) Co., Ltd. > > > Best regards,
diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 84a0789fad96a..bf8f2d8e9e2a1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -123,7 +123,7 @@ &pcie30phy { &pcie3x1 { num-lanes = <1>; pinctrl-names = "default"; - pinctrl-0 = <&pcie30x1m0_pins>; + pinctrl-0 = <&pcie30x1_reset_h>; reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_minipcie>; status = "okay"; @@ -148,6 +148,10 @@ pcie30x1_enable_h: pcie30x1-enable-h { rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; }; + pcie30x1_reset_h: pcie30x1-reset-h { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie30x2_reset_h: pcie30x2-reset-h { rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; };
to avoid conflict with sdmmc_det, change pci3x1 pinctrl-0 name. Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> --- Changes in v2: - new --- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)