| Message ID | 20241001042401.31903-6-ziyao@disroot.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Support clock and reset unit of Rockchip RK3528 | expand |
Hi, Am Dienstag, 1. Oktober 2024, 06:23:58 CEST schrieb Yao Zi: > RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE, > which should operate in normal mode only. Add corresponding definition > and handle it in code. > More commit message would be nice ;-) . It's the PPLL for the pcie controller that is specified in the manual to only work in normal mode. This is helpful for people reading along :-) . Heiko > Signed-off-by: Yao Zi <ziyao@disroot.org> > --- > drivers/clk/rockchip/clk-pll.c | 10 ++++++---- > drivers/clk/rockchip/clk.h | 2 ++ > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c > index 606ce5458f54..46be1c67301a 100644 > --- a/drivers/clk/rockchip/clk-pll.c > +++ b/drivers/clk/rockchip/clk-pll.c > @@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, > rockchip_rk3036_pll_get_params(pll, &cur); > cur.rate = 0; > > - cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); > - if (cur_parent == PLL_MODE_NORM) { > - pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); > - rate_change_remuxed = 1; > + if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { > + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); > + if (cur_parent == PLL_MODE_NORM) { > + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); > + rate_change_remuxed = 1; > + } > } > > /* update pll values */ > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index fd3b476dedda..1efc5c3a1e77 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -391,6 +391,7 @@ struct rockchip_pll_rate_table { > * Flags: > * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the > * rate_table parameters and ajust them if necessary. > + * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only > */ > struct rockchip_pll_clock { > unsigned int id; > @@ -408,6 +409,7 @@ struct rockchip_pll_clock { > }; > > #define ROCKCHIP_PLL_SYNC_RATE BIT(0) > +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) > > #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ > _lshift, _pflags, _rtable) \ >
On Wed, Oct 02, 2024 at 10:16:49AM +0200, Heiko Stübner wrote: > Hi, > > Am Dienstag, 1. Oktober 2024, 06:23:58 CEST schrieb Yao Zi: > > RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE, > > which should operate in normal mode only. Add corresponding definition > > and handle it in code. > > > > More commit message would be nice ;-) . Good idea. > It's the PPLL for the pcie controller that is specified in the manual to > only work in normal mode. This is helpful for people reading along :-) . > > Heiko btw, for the documentation, is there any technical reference manual of RK3528 available publicly? Please let me know if it's true, it will be quite helpful to understand clock tree better :) Thanks, Yao Zi
Am Mittwoch, 2. Oktober 2024, 12:08:20 CEST schrieb Yao Zi: > On Wed, Oct 02, 2024 at 10:16:49AM +0200, Heiko Stübner wrote: > > Hi, > > > > Am Dienstag, 1. Oktober 2024, 06:23:58 CEST schrieb Yao Zi: > > > RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE, > > > which should operate in normal mode only. Add corresponding definition > > > and handle it in code. > > > > > > > More commit message would be nice ;-) . > > Good idea. > > > It's the PPLL for the pcie controller that is specified in the manual to > > only work in normal mode. This is helpful for people reading along :-) . > > > > Heiko > > btw, for the documentation, is there any technical reference manual > of RK3528 available publicly? Please let me know if it's true, it will > be quite helpful to understand clock tree better :) Sadly not. So far there hasn't been a "leak" yet and Rockchip also seems to have gotten more restrictive for whatever strange reason, so with my NDA I also only got part1 of the manual. Heiko
On Wed, Oct 02, 2024 at 12:12:11PM +0200, Heiko Stübner wrote: > Am Mittwoch, 2. Oktober 2024, 12:08:20 CEST schrieb Yao Zi: > > On Wed, Oct 02, 2024 at 10:16:49AM +0200, Heiko Stübner wrote: > > btw, for the documentation, is there any technical reference manual > > of RK3528 available publicly? Please let me know if it's true, it will > > be quite helpful to understand clock tree better :) > > Sadly not. So far there hasn't been a "leak" yet and Rockchip also seems > to have gotten more restrictive for whatever strange reason, so with my > NDA I also only got part1 of the manual. Oops, sad but also much thanks. Best regards, Yao Zi
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 606ce5458f54..46be1c67301a 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll, rockchip_rk3036_pll_get_params(pll, &cur); cur.rate = 0; - cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); - if (cur_parent == PLL_MODE_NORM) { - pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); - rate_change_remuxed = 1; + if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) { + cur_parent = pll_mux_ops->get_parent(&pll_mux->hw); + if (cur_parent == PLL_MODE_NORM) { + pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); + rate_change_remuxed = 1; + } } /* update pll values */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..1efc5c3a1e77 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -391,6 +391,7 @@ struct rockchip_pll_rate_table { * Flags: * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the * rate_table parameters and ajust them if necessary. + * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only */ struct rockchip_pll_clock { unsigned int id; @@ -408,6 +409,7 @@ struct rockchip_pll_clock { }; #define ROCKCHIP_PLL_SYNC_RATE BIT(0) +#define ROCKCHIP_PLL_FIXED_MODE BIT(1) #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ _lshift, _pflags, _rtable) \
RK3528 comes with a new PLL type, flagged by ROCKCHIP_PLL_FIXED_MODE, which should operate in normal mode only. Add corresponding definition and handle it in code. Signed-off-by: Yao Zi <ziyao@disroot.org> --- drivers/clk/rockchip/clk-pll.c | 10 ++++++---- drivers/clk/rockchip/clk.h | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-)