| Message ID | 20250208015757.27594-2-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | clk: rockchip: Fixed some incorrect commits | expand |
diff --git a/arch/arm/boot/dts/rockchip/rk322x.dtsi b/arch/arm/boot/dts/rockchip/rk322x.dtsi index 96421355c274..2eb3c6611e59 100644 --- a/arch/arm/boot/dts/rockchip/rk322x.dtsi +++ b/arch/arm/boot/dts/rockchip/rk322x.dtsi @@ -667,6 +667,8 @@ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + assigned-clocks = <&cru DCLK_VOP>; + assigned-clock-parents = <&cru SCLK_HDMI_PHY>; resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; reset-names = "axi", "ahb", "dclk"; iommus = <&vop_mmu>;
If dclk_vop use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT we should assign clk parent in DT to make it extra clear that hdmiphy should be used as dclk_vop parent. Fixes: 1d34b9757523 ("clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228") Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- arch/arm/boot/dts/rockchip/rk322x.dtsi | 2 ++ 1 file changed, 2 insertions(+)