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b=vz9QGDTtxm2pH7WNpUnco3aKFP 45VuVhIFJxmM0zxWcaqz4tKnYriuvIPUDywQhhgA0NnMnq7m4oceeOlA7DDh7CK3hVLoyfpSvjbaN h2a2sneibS79NieSwNjnn2WvL4uGzdDKARkCGauHTNWwVXnS/Lj+JrLnQ2gORBcPLXbQl/qoLV9xK c/ymuiEIaan5fgFoPD9OTjCvNn074oBaZgdpatcjEpIvA5o2VgF9JizZl5EnTeaFrmhY9Z+b/YAJC K/ywni3cBV8CQYjPVl8q7hd74Z8+eGxhSuXvYgTsqMN6sW+IKIlZo2uTO5tTa93yUdtbyT1db2tw3 whJ8sCrg==; Received: from i53875bc0.versanet.de ([83.135.91.192] helo=localhost.localdomain) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1thcKe-0008Cw-Ei; Mon, 10 Feb 2025 23:32:48 +0100 From: Heiko Stuebner To: srinivas.kandagatla@linaro.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, detlev.casanova@collabora.com, sebastian.reichel@collabora.com Subject: [PATCH v2 6/6] arm64: dts: rockchip: add rk3576 otp node Date: Mon, 10 Feb 2025 23:32:19 +0100 Message-ID: <20250210223219.1193346-14-heiko@sntech.de> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250210223219.1193346-1-heiko@sntech.de> References: <20250210223219.1193346-1-heiko@sntech.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250210_223950_987481_B5ABBD5C X-CRM114-Status: GOOD ( 10.89 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org This adds the otp node to the rk3576 soc devicetree including the individual fields we know about. Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3576.dtsi | 39 ++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi index 4dde954043ef..29b47799849a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@ -1260,6 +1260,45 @@ sdhci: mmc@2a330000 { status = "disabled"; }; + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names = "otp", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpub_leakage: cpub-leakage@1e { + reg = <0x1e 0x1>; + }; + cpul_leakage: cpul-leakage@1f { + reg = <0x1f 0x1>; + }; + npu_leakage: npu-leakage@20 { + reg = <0x20 0x1>; + }; + gpu_leakage: gpu-leakage@21 { + reg = <0x21 0x1>; + }; + log_leakage: log-leakage@22 { + reg = <0x22 0x1>; + }; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>,