From patchwork Sat Feb 15 00:55:37 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cristian Ciocaltea X-Patchwork-Id: 13975846 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F75BC021A4 for ; Sat, 15 Feb 2025 00:59:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id :MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IBKzdube/rLuSY669wk78pKnhUa62apToFH5CKtTirU=; b=X6oto0YDsajpWd FJQLUGNxtHB/aO2bj4bFjD8qTUKEXHEqt61MPuXeNqfnHB2PFc+0BIsoP4tcvQr37x8urT6kUckAY XA/dHXWk2aTOBY+0q/F8mFMn9M+wP1PJonGCEvBz4N9R3Z5hErrRNgXFvDOUianxAzkYqtSZzEfK1 iuJ7JZu26D5NG+P5Aa96uN9EJbIXwkK8/Vx40sxm+j/TnEg3PU+26WOb0a0qgh/Mug3jmB6fmW8Bb TOVSpMzR+yBCL8yVIOWWOaTgiBqfwb2lY4kbFwy1gLhc5iWrmAsMkefBt8+wx26Ux8BRNp3eN/wNL RybzLyd0FzdecrajQVYw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1tj6WF-0000000GfqI-271C; Sat, 15 Feb 2025 00:58:55 +0000 Received: from bali.collaboradmins.com ([2a01:4f8:201:9162::2]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1tj6TM-0000000Gf1v-3syB; Sat, 15 Feb 2025 00:55:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739580955; bh=g4ZiNjBB56+mnqDk9Mu4uIOUw/V5PSViIE9EHg+P5Ss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pjmbm3Wg1oS7pYIFqz84AP0iP/Y3H9SiuKck4O7M+cykW0FWNskBKIlbXeSKER3MP cLDu5/Ujwfub5TR9NVnxISKz3jzh7/GbLmCQCEqycPR9r3QIqM2WDDg9Xk1GhCNJxa VRRWQi8cPmMMjz7fIMtEUc6a5gmKQ7R+XEbKYd4a9v7HVZafF00FwMcL0r2iLLxojg lf1RCv+55HHXjOCQfX48N8H4jYqccOV1xJFDv851ZalDN20ueVfQPG1QHZdDnwP0Gv EvvL64pqURZVMLbfcnK9nCpIPciz0gCHtu0qVI4pV8lBuAaMdy5so2lObCo13JG05c xDq86Gt4yNfJg== Received: from localhost (144.232.221.87.dynamic.jazztel.es [87.221.232.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id C4D1D17E0E95; Sat, 15 Feb 2025 01:55:54 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 15 Feb 2025 02:55:37 +0200 Subject: [PATCH 1/4] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI1 MIME-Version: 1.0 Message-Id: <20250215-vop2-hdmi1-disp-modes-v1-1-81962a7151d6@collabora.com> References: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> In-Reply-To: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250214_165557_115580_2CE04488 X-CRM114-Status: GOOD ( 16.19 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The RK3588 specific implementation is currently quite limited in terms of handling the full range of display modes supported by the connected screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a few of them. Additionally, it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of HDMI1 PHY PLL as a more accurate DCLK source to handle all display modes up to 4K@60Hz. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index afc946ead87091373605e59dbca281a9e91bea57..f1700b2fabf0b0d000cf3c9cf5f06ca791b87499 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -216,6 +216,7 @@ struct vop2 { struct clk *aclk; struct clk *pclk; struct clk *pll_hdmiphy0; + struct clk *pll_hdmiphy1; /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -2270,11 +2271,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, * Switch to HDMI PHY PLL as DCLK source for display modes up * to 4K@60Hz, if available, otherwise keep using the system CRU. */ - if (vop2->pll_hdmiphy0 && clock <= VOP2_MAX_DCLK_RATE) { + if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <= VOP2_MAX_DCLK_RATE) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI0) { + if (!vop2->pll_hdmiphy0) + break; + if (!vp->dclk_src) vp->dclk_src = clk_get_parent(vp->dclk); @@ -2284,6 +2288,20 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, "Could not switch to HDMI0 PHY PLL: %d\n", ret); break; } + + if (rkencoder->crtc_endpoint_id == ROCKCHIP_VOP2_EP_HDMI1) { + if (!vop2->pll_hdmiphy1) + break; + + if (!vp->dclk_src) + vp->dclk_src = clk_get_parent(vp->dclk); + + ret = clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI1 PHY PLL: %d\n", ret); + break; + } } } @@ -3733,6 +3751,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->pll_hdmiphy0); } + vop2->pll_hdmiphy1 = devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); + if (IS_ERR(vop2->pll_hdmiphy1)) { + drm_err(vop2->drm, "failed to get pll_hdmiphy1\n"); + return PTR_ERR(vop2->pll_hdmiphy1); + } + vop2->irq = platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n");