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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0OxQkhjMER0GI8R+xrs4r9TGwez+N2ImFM6XhLVnC+SNLtLQszp7hxLRqSCSU8I5b5VtJeNSQFfDAoJWAqTXEg/71mAmiAj65yj0ekDpIsmuayzHTavGiFtf73rA61l9atiNjnkARt3tzvXGNUpj7wDMhjD7A/UHQYLpc5ZttQvDEAsT1q4ek3ZsyAPCE79bbrFnyGObxg8hQ92WyfH4NzkReqiU3ZNkCwbsF8qkUuflX+WHD+uWsT01rQyPn+IcIeHm42RBKUNsZWNKEB8CfUFv1gGmD87nXvJ8BsarwpZOsCiDMDmgmGpYJrCm2goGSLE4MjnG6ZutAKIs5bUZmoHgKBtqYzyzXxR7Lka057anUOxil41yaOKFHAH0405SMFgx4NdPKT4w5sVrdVGB9C2MMdsTTWqUpSgHow24+H20OO+rX1X/Nodb0QTd9PLR3cNVFSJaKJhA4cxPKpqC+/x4LFYWTpeRMsuiPyHnVLhAhiT+vn/mFzRwzjcZWzd09XFjLnxU3YL1+S96l8H4G4Xec3m7DIQ6UCBnc0Y6eNuEbUvelr23cVelMUeLiagfCiKlb0skb1Jus8I6cs6c2dFLVam5yw4ELt35gJp5KT+iNpjzBiOE5RwQ4Dw0F9GZV+4pINsZIvFLaf77gEUVg/dKAoOcxoZFp1ZO3eXu8Z8K8ETqf+Sdd+XUIrllL0iB2vncImrUuwSKHm9Zjmh6kW1FNu+78BCNAf7kYEmmXxebQ2yTtJbYwpEDpod8Y65oW1cmL99UNlaj4/U61R263eNj0etCTRG/VGNDR5lBf0F5MAfIl8BHgi96Vnnp1OmZSO+as2cKaP80w3Bl6gtEafQNSSlWQ8tLh/YpLtDMuNNVDNWgc5QdVn9djLuFgUya1ap8ZyEkAAFjiUiGYgX8U0um86577enBCodRknWBLIDsB+mEBgenyerMRg+Vn+UZQ2oXJtm7yHX5i48mzpSzdJr5gKHNZyQe38Wourrnt4xfhjOM+Untu92vFLg0Mk94HtcM3dpIBX0udFxcLKqj+Gqyus5aOzTZEIL2HLr63cY2++INavvbFgP6sqkA5BHlE3QmfcncE48YFUKIGxwKaF9dXr8e0iQwm5CmMfSv+c3nK4izAwMSJ4BRvfeOyiF51ueYN/FuuTTPJ8e75N/WtVVIcPoWkRDB/0AE5dLZWCvJH9tcJWTZPuVzRtL3e/ETZEYaYuiOIQuDK8LDTFQhNlB2yVIhBB1vVz7UmgM+yCMEL53OALwQnh5I2eHyDij9pQcoayoFeYdEaIC3j+loNoHLI+vKVo2BEj6DZCNGtVQGt5M56UTNeYfi8zHFUviS0YjJY6t9eAHeOLMQvkZNKJExXyRh61Fjryn8dar+7bSBzcRJRQUFxk7XHRU0y86wC1ITXg7N4lPolB6OlJ2PylQDY3dTJzVbCgbdXO/h2ZKSsTefhwXIzXRM3phIqE89NVv8Cc3vOhdhQIeUYhPeCRTbEJRjFhFvTxb9MmnKyU7aqIO+vWCZoqd7in2Y3FAHqXdUrK6KCsRqQLjsPDdCeG7AvLPsqQuLtnHzfrdYrCdE5OJJuCf4d0W2x3ZbKDXh X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ad9c7fd9-57bc-4c69-16ad-08db4a6e5111 X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 May 2023 18:03:07.2131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: bsvS5XFLLaxuDyv6zvIk0PbV9Vgv6wrZE8pc2GNi4iEAG+vkqekq291Stzt0/V2f X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6457 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230501_110325_211324_969A47D1 X-CRM114-Status: GOOD ( 13.72 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org What omap does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Signed-off-by: Jason Gunthorpe --- drivers/iommu/omap-iommu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 537e402f9bba97..34340ef15241bc 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1555,16 +1555,31 @@ static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, omap_domain->dev = NULL; } -static void omap_iommu_set_platform_dma(struct device *dev) +static int omap_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + struct omap_iommu_domain *omap_domain; + if (domain == identity_domain || !domain) + return 0; + + omap_domain = to_omap_domain(domain); spin_lock(&omap_domain->lock); _omap_iommu_detach_dev(omap_domain, dev); spin_unlock(&omap_domain->lock); + return 0; } +static struct iommu_domain_ops omap_iommu_identity_ops = { + .attach_dev = omap_iommu_identity_attach, +}; + +static struct iommu_domain omap_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &omap_iommu_identity_ops, +}; + static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) { struct omap_iommu_domain *omap_domain; @@ -1732,11 +1747,11 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) } static const struct iommu_ops omap_iommu_ops = { + .identity_domain = &omap_iommu_identity_domain, .domain_alloc = omap_iommu_domain_alloc, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, - .set_platform_dma_ops = omap_iommu_set_platform_dma, .pgsize_bitmap = OMAP_IOMMU_PGSIZES, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = omap_iommu_attach_dev,