diff mbox series

ARM: dts: rockchip: fix rk3288 cpu opp node reference

Message ID AM3PR03MB0966C52CCF14FCEDE6615265AC790@AM3PR03MB0966.eurprd03.prod.outlook.com (mailing list archive)
State New, archived
Headers show
Series ARM: dts: rockchip: fix rk3288 cpu opp node reference | expand

Commit Message

Jonas Karlman Feb. 24, 2019, 9:51 p.m. UTC
The following error can be seen during boot:

  of: /cpus/cpu@501: Couldn't find opp node

Change cpu nodes to use operating-points-v2 in order to fix this.

Fixes: ce76de984649 ("ARM: dts: rockchip: convert rk3288 to operating-points-v2")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 arch/arm/boot/dts/rk3288.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Heiko Stuebner March 12, 2019, 8:52 a.m. UTC | #1
Am Sonntag, 24. Februar 2019, 22:51:22 CET schrieb Jonas Karlman:
> The following error can be seen during boot:
> 
>   of: /cpus/cpu@501: Couldn't find opp node
> 
> Change cpu nodes to use operating-points-v2 in order to fix this.
> 
> Fixes: ce76de984649 ("ARM: dts: rockchip: convert rk3288 to operating-points-v2")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

added a Cc-stable tag and applied as fix for 5.1

Thanks for catching this
Heiko
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index ca7d52daa8fb..09868dcee34b 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -70,7 +70,7 @@ 
 			compatible = "arm,cortex-a12";
 			reg = <0x501>;
 			resets = <&cru SRST_CORE1>;
-			operating-points = <&cpu_opp_table>;
+			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
 			clock-latency = <40000>;
 			clocks = <&cru ARMCLK>;
@@ -80,7 +80,7 @@ 
 			compatible = "arm,cortex-a12";
 			reg = <0x502>;
 			resets = <&cru SRST_CORE2>;
-			operating-points = <&cpu_opp_table>;
+			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
 			clock-latency = <40000>;
 			clocks = <&cru ARMCLK>;
@@ -90,7 +90,7 @@ 
 			compatible = "arm,cortex-a12";
 			reg = <0x503>;
 			resets = <&cru SRST_CORE3>;
-			operating-points = <&cpu_opp_table>;
+			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
 			clock-latency = <40000>;
 			clocks = <&cru ARMCLK>;