From patchwork Fri Mar 21 14:04:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seungwon Jeon X-Patchwork-Id: 3874601 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2D14BBF549 for ; Fri, 21 Mar 2014 14:04:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3963020213 for ; Fri, 21 Mar 2014 14:04:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3517E20279 for ; Fri, 21 Mar 2014 14:04:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965704AbaCUOEX (ORCPT ); Fri, 21 Mar 2014 10:04:23 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:26959 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965576AbaCUOEO (ORCPT ); Fri, 21 Mar 2014 10:04:14 -0400 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N2S00ET3HR1NLB0@mailout2.samsung.com>; Fri, 21 Mar 2014 23:04:13 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.51]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 20.45.12635.DD64C235; Fri, 21 Mar 2014 23:04:13 +0900 (KST) X-AuditID: cbfee68d-b7fcd6d00000315b-a1-532c46dd6818 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id C6.14.29263.CD64C235; Fri, 21 Mar 2014 23:04:12 +0900 (KST) Received: from DOTGIHJUN01 ([12.36.185.168]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N2S00CY0HR0L7A0@mmp2.samsung.com>; Fri, 21 Mar 2014 23:04:12 +0900 (KST) From: Seungwon Jeon To: linux-samsung-soc@vger.kernel.org, linux-mmc@vger.kernel.org Cc: 'Chris Ball' , 'Kukjin Kim' , 'Jaehoon Chung' , 'Ulf Hansson' , 'Alim Akhtar' Subject: [PATCH 4/7] mmc: dw_mmc: exynos: incorporate ciu_div into timing property Date: Fri, 21 Mar 2014 23:04:13 +0900 Message-id: <001e01cf450e$708644a0$5192cde0$%jun@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=utf-8 Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac9FDnBe8204S3LnRZ+znBxMUTrMMw== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrAIsWRmVeSWpSXmKPExsVy+t8zY927bjrBBoe+MVs8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWKyyYl NSezLLVI3y6BK+PztonMBeu0KubPe8vSwHhDqYuRk0NCwERi54RT7BC2mMSFe+vZuhi5OIQE ljFKTFl9GMjhACs6/TgKIj6dUWLCzR/sEM4fRomjW9ewgXSzCWhJ/H3zhhnEFhFwkHh3/QIT iM0scIJRYt5iYxBbWCBEYs42kDgHB4uAqsSKtwogYV4BW4kF884wQdiCEj8m32MBKWEWUJeY MiUXYoq8xOY1b5khzlGXePRXF2KRnkTXnj5WiBIRiX0v3jGCXCYhcIpdYuPD6ywgCRYBAYlv kw+xQPTKSmw6wAzxrqTEwRU3WCYwis1CsngWwuJZSBbPQrJhASPLKkbR1ILkguKk9CJDveLE 3OLSvHS95PzcTYyQ2OvdwXj7gPUhxmSg7ROZpUST84Gxm1cSb2hsZmRhamJqbGRuaUaasJI4 b9LDpCAhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjP0Surv+dxvty5rO1qD36HL3+TaGjf9+ cp2/HVEQdKKjTTXEPJLfQ+Tb57s8Lpd7tee/+pFlwWe7tfvj4X2qs35NdOs6ERj6NoTzV5sa 082uY/+lBf5sthWuFT912WR1dvaXff198yemXTA2CpmfPuV2n/HO57/uv0+IeuiRlfmuZpbC i0Q/ViWW4oxEQy3mouJEAEOZH3nTAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprLKsWRmVeSWpSXmKPExsVy+t9jQd07bjrBBhd32Fg8mLeNzWLC5e2M Fjd+tbFa9C64ymZx5H8/o8WM8/uYLI6vDXdg97hzbQ+bx41XC5k8+rasYvT4vEkugCWqgdEm IzUxJbVIITUvOT8lMy/dVsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB+gCJYWyxJxS oFBAYnGxkr4dpgmhIW66FjCNEbq+IUFwPUYGaCBhHWPG520TmQvWaVXMn/eWpYHxhlIXIweH hICJxOnHUV2MnECmmMSFe+vZuhi5OIQEpjNKTLj5gx3C+cMocXTrGjaQKjYBLYm/b94wg9gi Ag4S765fYAKxmQVOMErMW2wMYgsLhEjM2QYS5+BgEVCVWPFWASTMK2ArsWDeGSYIW1Dix+R7 LCAlzALqElOm5EJMkZfYvOYtM8Rp6hKP/upCLNKT6NrTxwpRIiKx78U7xgmMArOQDJqFMGgW kkGzkHQsYGRZxSiaWpBcUJyUnmuoV5yYW1yal66XnJ+7iREc2c+kdjCubLA4xCjAwajEw1vB qR0sxJpYVlyZe4hRgoNZSYS3004nWIg3JbGyKrUoP76oNCe1+BBjMtCXE5mlRJPzgUknryTe 0NjEzMjSyMzCyMTcnDRhJXHeA63WgUIC6YklqdmpqQWpRTBbmDg4pRoYc068yhH8+PDt+213 68Qcl6rtl5qz1/hGvVYkv/HJW7v0frXc9f1kU7eMMYdh95Idd5m2cm43/GoZv/WkTsGWoNvN 788UTrv7ad95q+BfARobrO+1m5184lo7M3wG+2blpHj30PXOT1ZqT/2Y3KVS/Jf/kulbh++f IuVv7POK+WW+9M41Y+klH5RYijMSDbWYi4oTAeEOvq0wAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP ciu_div may not be common value for all speed mode. So, it needs to be attached to CLKSEL timing. Signed-off-by: Seungwon Jeon --- drivers/mmc/host/dw_mmc-exynos.c | 75 ++++++++++++++++++++++++++------------ drivers/mmc/host/dw_mmc-exynos.h | 1 + 2 files changed, 53 insertions(+), 23 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 801861b..ce261c8 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -39,6 +39,7 @@ struct dw_mci_exynos_priv_data { u8 ciu_div; u32 sdr_timing; u32 ddr_timing; + u32 hs200_timing; u32 cur_speed; }; @@ -64,6 +65,18 @@ static struct dw_mci_exynos_compatible { }, }; +static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host) +{ + struct dw_mci_exynos_priv_data *priv = host->priv; + + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) + return EXYNOS4412_FIXED_CIU_CLK_DIV; + else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) + return EXYNOS4210_FIXED_CIU_CLK_DIV; + else + return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1; +} + static int dw_mci_exynos_priv_init(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; @@ -77,6 +90,8 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT); } + priv->ciu_div = dw_mci_exynos_get_ciu_div(host); + return 0; } @@ -90,7 +105,7 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host) else rate = clk_get_rate(host->ciu_clk); - host->bus_hz = rate / (priv->ciu_div + 1); + host->bus_hz = rate / priv->ciu_div; return 0; } @@ -156,9 +171,10 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) struct dw_mci_exynos_priv_data *priv = host->priv; unsigned int wanted = ios->clock; unsigned long actual; - u8 div = priv->ciu_div + 1; - if (ios->timing == MMC_TIMING_MMC_DDR52) { + if (ios->timing == MMC_TIMING_MMC_HS200) { + mci_writel(host, CLKSEL, priv->hs200_timing); + } else if (ios->timing == MMC_TIMING_MMC_DDR52) { mci_writel(host, CLKSEL, priv->ddr_timing); /* Should be double rate for DDR mode */ if (ios->bus_width == MMC_BUS_WIDTH_8) @@ -179,6 +195,7 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) wanted = EXYNOS_CCLKIN_MIN; if (wanted != priv->cur_speed) { + u8 div = dw_mci_exynos_get_ciu_div(host); int ret = clk_set_rate(host->ciu_clk, wanted * div); if (ret) dev_warn(host->dev, @@ -191,14 +208,34 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios) } } +static int dw_mci_exynos_dt_populate_timing(struct dw_mci *host, + unsigned int ctrl_type, + const char *propname, + u32 *out_values) +{ + struct device_node *np = host->dev->of_node; + u32 timing[3]; + int ret; + + ret = of_property_read_u32_array(np, propname, timing, 3); + if (ret) + return ret; + + if (ctrl_type == DW_MCI_TYPE_EXYNOS4412 || + ctrl_type == DW_MCI_TYPE_EXYNOS4210) + timing[2] = 0; + + *out_values = SDMMC_CLKSEL_TIMING(timing[0], timing[1], timing[2]); + + return 0; +} + + static int dw_mci_exynos_parse_dt(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv; struct device_node *np = host->dev->of_node; - u32 timing[2]; - u32 div = 0; - int idx; - int ret; + int idx, ret; priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL); if (!priv) { @@ -211,29 +248,21 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host) priv->ctrl_type = exynos_compat[idx].ctrl_type; } - if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) - priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1; - else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210) - priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1; - else { - of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div); - priv->ciu_div = div; - } - - ret = of_property_read_u32_array(np, - "samsung,dw-mshc-sdr-timing", timing, 2); + ret = dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type, + "samsung,dw-mshc-sdr-timing", &priv->sdr_timing); if (ret) return ret; - priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); - - ret = of_property_read_u32_array(np, - "samsung,dw-mshc-ddr-timing", timing, 2); + ret = dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type, + "samsung,dw-mshc-ddr-timing", &priv->ddr_timing); if (ret) return ret; - priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); + dw_mci_exynos_dt_populate_timing(host, priv->ctrl_type, + "samsung,dw-mshc-hs200-timing", &priv->hs200_timing); + host->priv = priv; + return 0; } diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h index a4c6e10..78b3f20 100644 --- a/drivers/mmc/host/dw_mmc-exynos.h +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -20,6 +20,7 @@ #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) +#define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7) #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ SDMMC_CLKSEL_CCLK_DIVIDER(z))