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Wed, 13 Sep 2023 13:44:03 +0000 Received: from LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::faf:4cd0:ae27:1073]) by LV2PR12MB5869.namprd12.prod.outlook.com ([fe80::faf:4cd0:ae27:1073%6]) with mapi id 15.20.6768.036; Wed, 13 Sep 2023 13:44:03 +0000 From: Jason Gunthorpe To: Andy Gross , Alim Akhtar , Bjorn Andersson , AngeloGioacchino Del Regno , Baolin Wang , Christophe Leroy , Gerald Schaefer , Heiko Stuebner , iommu@lists.linux.dev, Jernej Skrabec , Jonathan Hunter , Joerg Roedel , Kevin Tian , Konrad Dybcio , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-s390@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-tegra@vger.kernel.org, Russell King , linuxppc-dev@lists.ozlabs.org, Matthias Brugger , Matthew Rosato , Michael Ellerman , Nicholas Piggin , Orson Zhai , Rob Clark , Robin Murphy , Samuel Holland , Thierry Reding , Krishna Reddy , Chen-Yu Tsai , Will Deacon , Yong Wu , Chunyan Zhang Cc: Lu Baolu , Dmitry Osipenko , Jerry Snitselaar , Marek Szyprowski , Nicolin Chen , Niklas Schnelle , Steven Price , Thierry Reding Subject: [PATCH v8 13/24] iommu/omap: Implement an IDENTITY domain Date: Wed, 13 Sep 2023 10:43:46 -0300 Message-ID: <13-v8-81230027b2fa+9d-iommu_all_defdom_jgg@nvidia.com> In-Reply-To: <0-v8-81230027b2fa+9d-iommu_all_defdom_jgg@nvidia.com> References: X-ClientProxiedBy: MN2PR03CA0008.namprd03.prod.outlook.com (2603:10b6:208:23a::13) To LV2PR12MB5869.namprd12.prod.outlook.com (2603:10b6:408:176::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV2PR12MB5869:EE_|SA3PR12MB7923:EE_ X-MS-Office365-Filtering-Correlation-Id: 80be4208-358a-493b-5b0a-08dbb45f7c4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mPq0rn4iCgiBrihDLxaeIj0BwbwzOgeP2fSmjkZwTvA/ZeupnEp2nMCKuphNXx5LNcN7va2cEFqdlF0/ogIX74YP4AcX5pD03zflSuwLcSqynwZmBu+49enuvpsqM/mhKabVQTyreGdD+8v/CazB7SXgPL3H5Kenz+Xqgd7QKH85CXhug+iVen1LpzMohJEpgcx/onx9DLdvlJpnzXZoKK9VGP5+w+hqxF7DA8KOloZ2sgF/JQaT4G63oMqHpRGIQGowo3LV7YwDXye3KzyycpMiDDXPyvQZ+csbLSAnXGW7KksgnZUKeH74R1/z+fK/pCfsI1JYipVjYFBW0IuDl/fXVuHeOMkSddqQnmOIGN0zxSqOMjI6lJyAUrWqtkaMtyO0XEOnL+p2L/qonfsDHeRXQgyfq32Cm3daSCFCR41SCB8fNIbwUfqnYDnhd/39/KB5loyEa0IZGn2IaCKClrrYTiDbo/7a44Yaa1fz37EduYhUx9+dX8w7D0kqy9EbId7/g5iK4d6QDy2yNhjGmDLOpPpAG592HReBZ40FvO/HJ25RuZGbuCcH80nFrrwHyerE+yAPxjJ0WJV05MlDUsiodnyd9UVUc4w1DiS8LCRtop2PE+oQ97/PFC09X+/RX6wFwX7gT7AutVHSTQTnCdArOkuv2oMhSiXQDtRw5LJ3WsO+KagkEOyqtS1atKegTx0baW00vG3U1y/cbgJWfL7nrbyku58MHRQu2mF19JY8VzB66/mUs52xCf2cM464BmMjBhG0CjqjyN/VeePz1D1iKeq0hoyWV34fwbpV4zZB3L1tabn6vTIHfbRDg1UZMaDgaZ89u7LX4FfAaEauvTuXbsBdMnrGpeW+f7sQ6KQ3oriDwVjdcw0RxlPYtYTLw98P2bXo4b8X7cq0TIbFobnvdeNmDS5iMx0WLTQljosVEUErm0xoHatx8TOzCbIJ/cmvXPw2Ba0Kslv9jxChfBROIKSqnhrFMegV9cT8MuyIRycnnNYB7HCqFinYlDuv3vRRT5y4+ZBAPzN33k86u9m6+AbhxdIVSfjDw2eX28DC3b4w0EDLv70meLL9JiB5q7CgIN8djnd+Sxnwkd/D5CekLyGcnq9lrKlHkgviKt18Un9RRns8UVx6CsunlXLfEOwgClu6luIfCokhyQF+V4pJQ7TJg68ORAZoVeR1tALFNg1CRasG1xV8ndBP5A70O8WptqQ12jjfzxutZX8Du+5Rm/z3+AD1ajNI5QsLCJzG5pl5j1XQOqmFF36YnyWjcXieb7lpSyviNGVCmJsTmQGYfnqVfp8bXqejzzknR1oCqaoxpcdfJK/89lffUubebmwI/8JEAmhRaBFhhUPQP+gauU7tNVB4k2HWRzFHOEIAj4C8+5tQPOM3AMKR/+vHd8zd9suE7icGrTw4nhP+sUJyyWvkQcMTtP/DMQ6cDv6ng55bJlHVc0e5bmDVH7XoMmBUsQsKF+tQjzxMezj+ALOZTUOwsNer6G0PJolqcHuFJrCZzLh2YLF/idf34n4MppyEDpGaYpaZqkYC5bgZrUKpO0sCIjZdJH5eVXlpOEI/I+utL2WyuMt5DIMg3Q+e X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80be4208-358a-493b-5b0a-08dbb45f7c4c X-MS-Exchange-CrossTenant-AuthSource: LV2PR12MB5869.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Sep 2023 13:44:00.4899 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 88bzyXfZ7TAVPQwocI8Etj1n02P2SQMAKjUKy36C4sW5TQagoR/j4+1EFkyH1r1Z X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7923 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org What omap does during omap_iommu_set_platform_dma() is actually putting the iommu into identity mode. Move to the new core support for ARM_DMA_USE_IOMMU by defining ops->identity_domain. This driver does not support IOMMU_DOMAIN_DMA, however it cannot be compiled on ARM64 either. Most likely it is fine to support dma-iommu.c Reviewed-by: Lu Baolu Reviewed-by: Jerry Snitselaar Signed-off-by: Jason Gunthorpe --- drivers/iommu/omap-iommu.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c index 537e402f9bba97..34340ef15241bc 100644 --- a/drivers/iommu/omap-iommu.c +++ b/drivers/iommu/omap-iommu.c @@ -1555,16 +1555,31 @@ static void _omap_iommu_detach_dev(struct omap_iommu_domain *omap_domain, omap_domain->dev = NULL; } -static void omap_iommu_set_platform_dma(struct device *dev) +static int omap_iommu_identity_attach(struct iommu_domain *identity_domain, + struct device *dev) { struct iommu_domain *domain = iommu_get_domain_for_dev(dev); - struct omap_iommu_domain *omap_domain = to_omap_domain(domain); + struct omap_iommu_domain *omap_domain; + if (domain == identity_domain || !domain) + return 0; + + omap_domain = to_omap_domain(domain); spin_lock(&omap_domain->lock); _omap_iommu_detach_dev(omap_domain, dev); spin_unlock(&omap_domain->lock); + return 0; } +static struct iommu_domain_ops omap_iommu_identity_ops = { + .attach_dev = omap_iommu_identity_attach, +}; + +static struct iommu_domain omap_iommu_identity_domain = { + .type = IOMMU_DOMAIN_IDENTITY, + .ops = &omap_iommu_identity_ops, +}; + static struct iommu_domain *omap_iommu_domain_alloc(unsigned type) { struct omap_iommu_domain *omap_domain; @@ -1732,11 +1747,11 @@ static struct iommu_group *omap_iommu_device_group(struct device *dev) } static const struct iommu_ops omap_iommu_ops = { + .identity_domain = &omap_iommu_identity_domain, .domain_alloc = omap_iommu_domain_alloc, .probe_device = omap_iommu_probe_device, .release_device = omap_iommu_release_device, .device_group = omap_iommu_device_group, - .set_platform_dma_ops = omap_iommu_set_platform_dma, .pgsize_bitmap = OMAP_IOMMU_PGSIZES, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = omap_iommu_attach_dev,