From patchwork Mon Mar 11 19:00:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 2249941 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 30E62DF5B1 for ; Mon, 11 Mar 2013 19:01:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754455Ab3CKTBH (ORCPT ); Mon, 11 Mar 2013 15:01:07 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:57330 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754427Ab3CKTBF (ORCPT ); Mon, 11 Mar 2013 15:01:05 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MJI00MNVFHIVX60@mailout4.samsung.com>; Tue, 12 Mar 2013 04:01:04 +0900 (KST) X-AuditID: cbfee61a-b7fa86d0000045ae-83-513e29f08a2b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id AA.FF.17838.0F92E315; Tue, 12 Mar 2013 04:01:04 +0900 (KST) Received: from amdc1344.digital.local ([106.116.147.32]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MJI00F2XFGXUP00@mmp2.samsung.com>; Tue, 12 Mar 2013 04:01:04 +0900 (KST) From: Sylwester Nawrocki To: linux-media@vger.kernel.org Cc: kyungmin.park@samsung.com, myungjoo.ham@samsung.com, shaik.samsung@gmail.com, arun.kk@samsung.com, a.hajda@samsung.com, linux-samsung-soc@vger.kernel.org, Sylwester Nawrocki Subject: [PATCH RFC 05/11] s5p-fimc: Add support for PIXELASYNCMx clocks Date: Mon, 11 Mar 2013 20:00:20 +0100 Message-id: <1363028426-2771-6-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1363028426-2771-1-git-send-email-s.nawrocki@samsung.com> References: <1363028426-2771-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnluLIzCtJLcpLzFFi42I5/e+xoO4HTbtAg/OrFS1urTvHavHx1G1W i7NNb9gtejZsZbWYcX4fk8XtxhVsFofftLNarNs5id2Bw2PnrLvsHn1bVjF6fN4kF8AcxWWT kpqTWZZapG+XwJUxr+0Fc8FmyYoN924xNjB+E+li5OSQEDCRWHR1AyOELSZx4d56ti5GLg4h gemMEocOHWCCcDqYJL4e/cEGUsUmYCjRe7QPrENEQF7iSe8NsA5mgXOMEm9uvGYFSQgLeEjc uT8PrIFFQFXix7JpYDavgKvEmZZHQDUcQOsUJOZMsgEJcwq4Sax5sgCsRAio5MfPM+wTGHkX MDKsYhRNLUguKE5KzzXUK07MLS7NS9dLzs/dxAgOpmdSOxhXNlgcYhTgYFTi4VX8ZhsoxJpY VlyZe4hRgoNZSYR35SabQCHelMTKqtSi/Pii0pzU4kOM0hwsSuK8B1qtA4UE0hNLUrNTUwtS i2CyTBycUg2MQW9lbKZtbj9gvkL54pHTG4UvPn7G6C2mP0nFylZtE3vPaauvbIw7qwrurGH+ yS/fHrWBQynk2m6GQ1WfLtdXmV3stIt0ZZvusXuayEYjuYdJX7Y9K2JprUwwMJiqcsa5ktWN 40q5T8AmcQXLhEDJv8fCjmidvf2kSCuzJKBy1qtKv801n1yVWIozEg21mIuKEwFkooUZIgIA AA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch ads handling of clocks for the CAMBLK subsystem which is a glue logic for FIMC-IS or LCD controller and FIMC IP. Signed-off-by: Sylwester Nawrocki Signed-off-by: Kyungmin Park --- drivers/media/platform/s5p-fimc/fimc-mdevice.c | 41 +++++++++++++++++++++++- drivers/media/platform/s5p-fimc/fimc-mdevice.h | 8 +++++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.c b/drivers/media/platform/s5p-fimc/fimc-mdevice.c index 0a7c95b..b9f9976 100644 --- a/drivers/media/platform/s5p-fimc/fimc-mdevice.c +++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.c @@ -944,7 +944,7 @@ static int fimc_md_create_links(struct fimc_md *fmd) } /* - * The peripheral sensor clock management. + * The peripheral sensor and CAM_BLK (PIXELASYNCMx) clocks management. */ static void fimc_md_put_clocks(struct fimc_md *fmd) { @@ -957,6 +957,17 @@ static void fimc_md_put_clocks(struct fimc_md *fmd) clk_put(fmd->camclk[i].clock); fmd->camclk[i].clock = ERR_PTR(-EINVAL); } + + /* Writeback (PIXELASYNCMx) clocks */ + for (i = 0; i < FIMC_MAX_WBCLKS; i++) { + if (IS_ERR(fmd->wbclk[i])) + continue; + /* FIXME: find better place to disable this clock! */ + clk_disable(fmd->wbclk[i]); + clk_unprepare(fmd->wbclk[i]); + clk_put(fmd->wbclk[i]); + fmd->wbclk[i] = ERR_PTR(-EINVAL); + } } static int fimc_md_get_clocks(struct fimc_md *fmd) @@ -993,6 +1004,34 @@ static int fimc_md_get_clocks(struct fimc_md *fmd) if (ret) fimc_md_put_clocks(fmd); + if (!fmd->use_isp) + return 0; + /* + * For now get only PIXELASYNCM1 clock (Writeback B/ISP), + * leave PIXELASYNCM0 out for the display driver. + */ + for (i = CLK_IDX_WB_B; i < FIMC_MAX_WBCLKS; i++) { + snprintf(clk_name, sizeof(clk_name), "pxl_async%u", i); + clock = clk_get(dev, clk_name); + if (IS_ERR(clock)) { + v4l2_err(&fmd->v4l2_dev, "Failed to get clock: %s\n", + clk_name); + ret = PTR_ERR(clock); + break; + } + ret = clk_prepare(clock); + if (ret < 0) { + clk_put(clock); + fmd->wbclk[i] = ERR_PTR(-EINVAL); + break; + } + fmd->wbclk[i] = clock; + /* FIXME: find better place to enable this clock! */ + clk_enable(clock); + } + if (ret) + fimc_md_put_clocks(fmd); + return ret; } diff --git a/drivers/media/platform/s5p-fimc/fimc-mdevice.h b/drivers/media/platform/s5p-fimc/fimc-mdevice.h index 5d6146e..91be5db 100644 --- a/drivers/media/platform/s5p-fimc/fimc-mdevice.h +++ b/drivers/media/platform/s5p-fimc/fimc-mdevice.h @@ -41,6 +41,13 @@ #define FIMC_MAX_SENSORS 8 #define FIMC_MAX_CAMCLKS 2 +/* LCD/ISP Writeback clocks (PIXELASYNCMx) */ +enum { + CLK_IDX_WB_A, + CLK_IDX_WB_B, + FIMC_MAX_WBCLKS +}; + struct fimc_csis_info { struct v4l2_subdev *sd; int id; @@ -87,6 +94,7 @@ struct fimc_md { struct fimc_sensor_info sensor[FIMC_MAX_SENSORS]; int num_sensors; struct fimc_camclk_info camclk[FIMC_MAX_CAMCLKS]; + struct clk *wbclk[FIMC_MAX_WBCLKS]; struct fimc_lite *fimc_lite[FIMC_LITE_MAX_DEVS]; struct fimc_dev *fimc[FIMC_MAX_DEVS]; struct media_device media_dev;