From patchwork Wed Mar 27 11:02:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2349521 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 78332DFE82 for ; Wed, 27 Mar 2013 11:07:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752202Ab3C0LHl (ORCPT ); Wed, 27 Mar 2013 07:07:41 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:33029 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751950Ab3C0LHk (ORCPT ); Wed, 27 Mar 2013 07:07:40 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MKB00E2ZG8RA3N0@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 27 Mar 2013 20:07:39 +0900 (KST) X-AuditID: cbfee61a-b7fa86d0000045ae-4e-5152d2fbf147 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id A1.3B.17838.BF2D2515; Wed, 27 Mar 2013 20:07:39 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MKB00EJ7G19TVH0@mmp2.samsung.com>; Wed, 27 Mar 2013 20:07:39 +0900 (KST) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, kyungmin.park@samsung.com, kgene.kim@samsung.com, m.szyprowski@samsung.com, t.figa@samsung.com, s.nawrocki@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, a.hajda@samsung.com, l.majewski@samsung.com Subject: [PATCH 15/21] clk: samsung: exynos4: Use SRC_MASK_PERIL{0,1} definitions Date: Wed, 27 Mar 2013 12:02:52 +0100 Message-id: <1364382178-25248-16-git-send-email-t.figa@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1364382178-25248-1-git-send-email-t.figa@samsung.com> References: <1364382178-25248-1-git-send-email-t.figa@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrILMWRmVeSWpSXmKPExsVy+t9jQd3fl4ICDeatVbW4te4cq0Xvgqts Fmeb3rBbvHm4mdFi0+NrrBYzzu9jslh75C67xdMJF9ksDr9pZ7VYP+M1i8WxGUsYHbg97lzb w+axeUm9R9+WVYwenzfJBbBEcdmkpOZklqUW6dslcGX0dPxmK7glW3Hx5h7GBsYNkl2MnBwS AiYSt/efZ4WwxSQu3FvP1sXIxSEkMJ1RYveRa0wgCSGBLiaJBy8yQGw2ATWJzw2P2EBsEQFV ic9tC9hBbGaBViaJhectQWxhgWCJO98PgQ1lAar5dOEMM4jNK+As8eTHLmaIZfIST+/3gc3h BIq/m36EEWKXk8SNN09ZJzDyLmBkWMUomlqQXFCclJ5rqFecmFtcmpeul5yfu4kRHHDPpHYw rmywOMQowMGoxMM7gyEoUIg1say4MvcQowQHs5IIr9EBoBBvSmJlVWpRfnxRaU5q8SFGaQ4W JXHeA63WgUIC6YklqdmpqQWpRTBZJg5OqQbGY4n2ecubdi6o51/5U4Dl9JE915e9E1X6bD29 5aNUmGsP010T72fvltZuTdQSSTQXkVMoCkx8K/U22y1NTYH79dbP9Tv+Fx3afTZ299rgl35V O2W+8tu87Nz+PYY1eMXyXfMfbt/dzG22usnnb8DU84Yrf4ku9hCLcd30L1dB1DXy1m+1pe/t lViKMxINtZiLihMBXNlFqTQCAAA= Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers, but they are not used for clock definitions. This patch modifies related clock definitions to use defined macros instead of numeric offsets. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 8ce3b25..e7c6acd 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -549,7 +549,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { * of the clocks can be removed. */ GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), - GATE(sclk_spdif, "sclk_spdif", "mout_spdif", 0xc354, 8, 0, 0), + GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), @@ -575,7 +575,7 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0), - GATE(sclk_audio1, "sclk_audio1", "div_audio1", 0xc354, 0, + GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, CLK_SET_RATE_PARENT, 0), GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), @@ -613,23 +613,31 @@ struct samsung_gate_clock exynos4_gate_clks[] __initdata = { GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"), GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0", - 0xc350, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), + SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT, + 0, "clk_uart_baud0"), GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1", - 0xc350, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), + SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT, + 0, "clk_uart_baud0"), GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2", - 0xc350, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), + SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT, + 0, "clk_uart_baud0"), GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3", - 0xc350, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), + SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT, + 0, "clk_uart_baud0"), GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4", - 0xc350, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), - GATE(sclk_audio2, "sclk_audio2", "div_audio2", 0xc354, 4, + SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT, + 0, "clk_uart_baud0"), + GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, CLK_SET_RATE_PARENT, 0), GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", - 0xc354, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), + SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT, + 0, "spi_busclk0"), GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", - 0xc354, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), + SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT, + 0, "spi_busclk0"), GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", - 0xc354, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), + SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT, + 0, "spi_busclk0"), GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", GATE_IP_CAM, 0, 0, 0, "fimc"), GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160",